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p80c31x2/32x2 p80c51x2/52x2/54x2/58x2 p87c51x2/52x2/54x2/58x2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp 128b/256b ram low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) product data supersedes data of 2002 sep 12 2003 jan 24 integrated circuits philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2 2003 jan 24 853-2337 29260 description the philips microcontrollers described in this data sheet are high-performance static 80c51 designs incorporating philips' high-density cmos technology with operation from 2.7 v to 5.5 v. they support both 6-clock and 12-clock operation. the p8xc31x2/51x2 and p8xc32x2/52x2/54x2/58x2 contain 128 byte ram and 256 byte ram respectively, 32 i/o lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial i/o port for either multi-processor communications, i/o expansion or full duplex uart, and on-chip oscillator and clock circuits. in addition, the devices are low power static designs which offer a wide range of operating frequencies down to zero. two software selectable modes of power reduction e idle mode and power-down mode e are available. the idle mode freezes the cpu while allowing the ram, timers, serial port, and interrupt system to continue functioning. the power-down mode saves the ram contents but freezes the oscillator, causing all other chip functions to be inoperative. since the design is static, the clock can be stopped without loss of user data. then the execution can be resumed from the point the clock was stopped. selection table for applications requiring more rom and ram, as well as more on-chip peripherals, see the p89c66x and p89c51rx2 data sheets. type memory timers serial interfaces ram rom otp flash # of timers pwm pca wd uart i 2 c can spi adc bits/ch. i/o pins interrupts (external) program security default clock rate optional clock rate max. freq. at 6-clk / 12-clk (mhz) freq. range at 3v (mhz) freq. range at 5v (mhz) p87c58x2 256b 32k 3 32 6 (2) 12clk 6-clk 30/33 016 030/33 p80c58x2 256b 32k 3 32 6 (2) 12clk 6-clk 30/33 016 030/33 p87c54x2 256b 16k 3 32 6 (2) 12clk 6-clk 30/33 016 030/33 p80c54x2 256b 16k 3 32 6 (2) 12clk 6-clk 30/33 016 030/33 p87c52x2 256b 8k 3 32 6 (2) 12clk 6-clk 30/33 016 030/33 p80c52x2 256b 8k 3 32 6 (2) 12clk 6-clk 30/33 016 030/33 p87c51x2 128b 4k 3 32 6 (2) 12clk 6-clk 30/33 016 030/33 p80c51x2 128b 4k 3 32 6 (2) 12clk 6-clk 30/33 016 030/33 p80c32x2 256b 3 32 6 (2) 12clk 6-clk 30/33 016 030/33 p80c31x2 128b 3 32 6 (2) 12clk 6-clk 30/33 016 030/33 note: 1. i 2 c = inter-integrated circuit bus; can = controller area network; spi = serial peripheral interface; pca = programmable counter array; adc = analog-to-digital converter; pwm = pulse width modulation philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 3 features ? 80c51 central processing unit 4 kbytes rom/eprom (p80/p87c51x2) 8 kbytes rom/eprom (p80/p87c52x2) 16 kbytes rom/eprom (p80/p87c54x2) 32 kbytes rom/eprom (p80/p87c58x2) 128 byte ram (p80/p87c51x2 and p80c31x2) 256 byte ram (p80/p87c52/54x2/58x2 and p80c32x2) boolean processor fully static operation low voltage (2.7 v to 5.5 v at 16 mhz) operation ? 12-clock operation with selectable 6-clock operation (via software or via parallel programmer) ? memory addressing capability up to 64 kbytes rom and 64 kbytes ram ? power control modes: clock can be stopped and resumed idle mode power-down mode ? cmos and ttl compatible ? two speed ranges at v cc = 5 v 0 to 30 mhz with 6-clock operation 0 to 33 mhz with 12-clock operation ? plcc, dip, tssop or lqfp packages ? extended temperature ranges ? dual data pointers ? security bits: rom (2 bits) otp (3 bits) ? encryption array - 64 bytes ? four interrupt priority levels ? six interrupt sources ? four 8-bit i/o ports ? full-duplex enhanced uart framing error detection automatic address recognition ? three 16-bit timers/counters t0, t1 (standard 80c51) and additional t2 (capture and compare) ? programmable clock-out pin ? asynchronous port reset ? low emi (inhibit ale, slew rate controlled outputs, and 6-clock mode) ? wake-up from power down by an external interrupt. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 4 p80c31/32x2 ordering information (romless) type number package temperature r( c) name description version range ( c) p80c31x2ba plcc44 plastic leaded chip carrier; 44 leads sot187-2 0 to +70 p80c31x2bn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 0 to +70 p80c32x2ba plcc44 plastic leaded chip carrier; 44 leads sot187-2 0 to +70 p80c32x2bn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 0 to +70 p80c32x2bbd lqfp44 plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1 0 to +70 p80c32x2fa plcc44 plastic leaded chip carrier; 44 leads sot187-2 40 to +85 p80c32x2fn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 40 to +85 p87c51x2 ordering information (4 kbyte otp) type number package temperature r( c) name description version range ( c) p87c51x2ba plcc44 plastic leaded chip carrier; 44 leads sot187-2 0 to +70 p87c51x2bn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 0 to +70 p87c51x2bbd lqfp44 plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1 0 to +70 p87c51x2fa plcc44 plastic leaded chip carrier; 44 leads sot187-2 40 to +85 p87c51x2fbd lqfp44 plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1 40 to +85 p87c52x2 ordering information (8 kbyte otp) type number package temperature r( c) name description version range ( c) p87c52x2ba plcc44 plastic leaded chip carrier; 44 leads sot187-2 0 to +70 p87c52x2bn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 0 to +70 p87c52x2bbd lqfp44 plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1 0 to +70 p87c52x2fa plcc44 plastic leaded chip carrier; 44 leads sot187-2 40 to +85 p87c52x2fn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 40 to +85 p87c52x2fbd lqfp44 plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1 40 to +85 p87c54x2 ordering information (16 kbyte otp) type number package temperature r( c) name description version range ( c) p87c54x2ba plcc44 plastic lead chip carrier; 44 leads sot187-2 0 to +70 p87c54x2bn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 0 to +70 p87c54x2bbd lqfp44 plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1 0 to +70 p87c54x2bdh tssop38 plastic thin shrink small outline package; 38 leads; body width 4.4 mm; lead pitch 0.5 mm sot510-1 0 to +70 p87c54x2fa plcc44 plastic lead chip carrier; 44 leads sot187-2 40 to +85 p87c54x2fbd lqfp44 plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1 40 to +85 p87c58x2 ordering information (32 kbyte otp) type number package temperature r( c) name description version range ( c) p87c58x2ba plcc44 plastic lead chip carrier; 44 leads sot187-2 0 to +70 p87c58x2bn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 0 to +70 p87c58x2bbd lqfp44 plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1 0 to +70 P87C58X2FA plcc44 plastic lead chip carrier; 44 leads sot187-2 40 to +85 p87c58x2fbd lqfp44 plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1 40 to +85 p87c58x2fn dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 40 to +85 all otp parts listed here are also available as rom parts (80c5xx2). please contact your philips representative if you would li ke to order a rom part. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 5 part number derivation memory temperature range package p87c51x2 7 = otp 0 = rom or romless 5 = rom/otp 3 = romless 1 = 128 bytes ram 4 kbytes rom/otp 2 = 256 bytes ram 8 kbytes rom/otp 4 = 256 bytes ram 16 kbytes rom/otp 8 = 256 bytes ram 32 kbytes rom/otp x2 = 6-clock mode available b = 0 c to +70 c f = 40 c to +85 c a = plcc n = dip bd = lqfp dh = tssop the following table illustrates the correlation between operating mode, power supply and maximum external clock frequency: operating mode power supply maximum clock frequency 6-clock 5 v 10% 30 mhz 6-clock 2.7 v to 5.5 v 16 mhz 12-clock 5 v 10% 33 mhz 12-clock 2.7 v to 5.5 v 16 mhz philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 6 block diagram 1 su01579 accelerated 80c51 cpu (12-clk mode, 6-clk mode) 0k / 4k / 8k / 16k / 32 kbyte code rom / eprom 128 / 256 byte data ram port 3 configurable i/os port 2 configurable i/os port 1 configurable i/os port 0 configurable i/os oscillator crystal or resonator full-duplex enhanced uart timer 0 timer 1 timer 2 philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 7 block diagram 2 (cpu-oriented) su01723 psen ea / v pp ale/prog rst xtal1 xtal2 v cc v ss port 0 drivers port 2 drivers ram addr register ram port 0 latch port 2 latch rom/eprom register b acc stack pointer tmp2 tmp1 alu timing and control instruction register pd oscillator psw port 1 latch port 3 latch port 1 drivers port 3 drivers program address register buffer pc incre- menter program counter dptr's multiple p1.0p1.7 p3.0p3.7 1 p0.0p0.7 p2.0p2.7 sfrs timers 8 8 16 note: 1. p3.2 and p3.5 absent in the tssop38 package. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 8 logic symbol port 0 port 1 port 2 port 3 address and data bus address bus t2 t2ex rxd txd int0 1 int1 t0 t1 1 wr rd secondary functions rst ea /v pp psen ale/prog v ss v cc xtal1 xtal2 su01724 note: 1. int0 /p3.2 and t1/p3.5 are absent in the tssop38 package. plastic dual in-line package pin configurations su01063 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 t2/p1.0 t2ex/p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 rst rxd/p3.0 txd/p3.1 int0 /p3.2 int1 /p3.3 t0/p3.4 t1/p3.5 p1.7 wr /p3.6 rd /p3.7 xtal2 xtal1 v ss p2.0/a8 p2.1/a9 p2.2/a10 p2.3/a11 p2.4/a12 p2.5/a13 p2.6/a14 p2.7/a15 psen ale ea /v pp p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 v cc dual in-line package philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 9 plastic leaded chip carrier pin functions su01062 plcc 6140 7 17 39 29 18 28 pin function 1 nic* 2 p1.0/t2 3 p1.1/t2ex 4 p1.2 5 p1.3 6 p1.4 7 p1.5 8 p1.6 9 p1.7 10 rst 11 p3.0/rxd 12 nic* 13 p3.1/txd 14 p3.2/int0 15 p3.3/int1 pin function 16 p3.4/t0 17 p3.5/t1 18 p3.6/wr 19 p3.7/rd 20 xtal2 21 xtal1 22 v ss 23 nic* 24 p2.0/a8 25 p2.1/a9 26 p2.2/a10 27 p2.3/a11 28 p2.4/a12 29 p2.5/a13 30 p2.6/a14 pin function 31 p2.7/a15 32 psen 33 ale 34 nic* 35 ea /v pp 36 p0.7/ad7 37 p0.6/ad6 38 p0.5/ad5 39 p0.4/ad4 40 p0.3/ad3 41 p0.2/ad2 42 p0.1/ad1 43 p0.0/ad0 44 v cc * no internal connection low profile quad flat pack pin functions su01487 lqfp 44 34 1 11 33 23 12 22 pin function 1 p1.5 2 p1.6 3 p1.7 4 rst 5 p3.0/rxd 6 nic* 7 p3.1/txd 8 p3.2/int0 9 p3.3/int1 10 p3.4/t0 11 p3.5/t1 12 p3.6/wr 13 p3.7/rd 14 xtal2 15 xtal1 pin function 16 v ss 17 nic* 18 p2.0/a8 19 p2.1/a9 20 p2.2/a10 21 p2.3/a11 22 p2.4/a12 23 p2.5/a13 24 p2.6/a14 25 p2.7/a15 26 psen 27 ale 28 nic* 29 ea /v pp 30 p0.7/ad7 pin function 31 p0.6/ad6 32 p0.5/ad5 33 p0.4/ad4 34 p0.3/ad3 35 p0.2/ad2 36 p0.1/ad1 37 p0.0/ad0 38 v cc 39 nic* 40 p1.0/t2 41 p1.1/t2ex 42 p1.2 43 p1.3 44 p1.4 * no internal connection plastic thin shrink small outline pack pin functions su01725 pin function 1 p3.0/rxd 2 p3.1/txd 3 p3.3/int1 4 p3.4/t0 5 p3.6/wr 6 p3.7/rd 7 xtal2 8 xtal1 9v ss 10 p2.0/a8 11 p2.1/a9 12 p2.2/a10 13 p2.3/a11 pin function 14 p2.4/a12 15 p2.5/a13 16 p2.6/a14 17 p2.7/a15 18 psen 19 ale/prog 20 ea /v pp 21 p0.7/ad7 22 p0.6/ad6 23 p0.5/ad5 24 p0.4/ad4 25 p0.3/ad3 26 p0.2/ad2 pin function 27 p0.1/ad1 28 p0.0/ad0 29 v dd 30 p1.0/t2 31 p1.1/t2ex 32 p1.2 33 p1.3 34 p1.4 35 p1.5 36 p1.6 37 p1.7 38 rst 1 19 20 38 tssop philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 10 pin descriptions pin number mnemonic dip plcc lqfp tssop type name and function v ss 20 22 16 9 i ground: 0 v reference. v cc 40 44 38 29 i power supply: this is the power supply voltage for normal, idle, and power-down operation. p0.0-0.7 3932 4336 3730 2821 i/o port 0: port 0 is an open-drain, bidirectional i/o port. port 0 pins that have 1s written to them float and can be used as high-impedance inputs. port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. in this application, it uses strong internal pull-ups when emitting 1s. port 0 also outputs the code bytes during program verification and received code bytes during eprom programming. external pull-ups are required during program verification. p1.0p1.7 18 29 4044, 13 3037 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 1 also receives the low-order address byte during program memory verification. alternate functions for port 1 include: 1 2 40 30 i/o t2 (p1.0): timer/counter 2 external count input/clockout (see programmable clock-out) 2 3 41 31 i t2ex (p1.1): timer/counter 2 reload/capture/direction control p2.0p2.7 2128 2431 1825 1017 i/o port 2: port 2 is an 8-bit bidirectional i/o port with internal pull-ups. port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (movx @dptr). in this application, it uses strong internal pull-ups when em itting 1s. during accesses to external data memory that use 8-bit addresses (mov @ri), port 2 emits the contents of the p2 special function register. some port 2 pins receive the high order address bits during eprom programming and verification. p3.0p3.7 1017 11, 1319 5, 713 16 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also serves the special features of the 80c51 family, as listed below: 10 11 5 1 i rxd (p3.0): serial input port 11 13 7 2 o txd (p3.1): serial output port 12 14 8 i int0 (p3.2): external interrupt 1 13 15 9 3 i int1 (p3.3): external interrupt 14 16 10 4 i t0 (p3.4): timer 0 external input 15 17 11 i t1 (p3.5): timer 1 external input 1 16 18 12 5 o wr (p3.6): external data memory write strobe 17 19 13 6 o rd (p3.7): external data memory read strobe rst 9 10 4 38 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc . ale/prog 30 33 27 19 o address latch enable/program pulse: output pulse for latching the low byte of the address during an access to external memory. in normal operation, ale is emitted at a constant rate of 1/6 (12-clock mode) or 1/3 (6-clock mode) the oscillator frequency, and can be used for external timing or clocking. note that one ale pulse is skipped during each access to external data memory. this pin is also the program pulse input (prog ) during eprom programming. ale can be disabled by setting sfr auxiliary.0. with this bit set, ale will be active only during a movx instruction. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 11 pin number mnemonic name and function type tssop lqfp plcc dip psen 29 32 26 18 o program store enable: the read strobe to external program memory. when the device is executing code from the external program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to external data memory. psen is not activated during fetches from internal program memory. ea /v pp 31 35 29 20 i external access enable/programming supply voltage: ea must be externally held low to enable the device to fetch code from external program memory locations 0000h to 0fffh/1fffh/3fffh/7fffh. if ea is held high, the device executes from internal program memory unless the program counter contains an address greater than the on-chip rom/otp. this pin also receives the 12.75 v programming supply voltage (v pp ) during eprom programming. if security bit 1 is programmed, ea will be internally latched on reset. xtal1 19 21 15 8 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. xtal2 18 20 14 7 o crystal 2: output from the inverting oscillator amplifier. notes: to avoid alatch-upo effect at power-on, the voltage on any pin at any time must not be higher than v cc + 0.5 v or v ss 0.5 v, respectively. 1. absent in the tssop38 package. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 12 table 1. special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h auxr# auxiliary 8eh ao xxxxxxx0b auxr1# auxiliary 1 a2h lpep 2 wupd 0 dps xxx000x0b b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h ckcon clock control register 8fh x2 xxx00000b dptr: data pointer (2 bytes) dph data pointer high 83h 00h dpl data pointer low 82h 00h af ae ad ac ab aa a9 a8 ie* interrupt enable a8h ea et2 es et1 ex1 et0 ex0 0x000000b bf be bd bc bb ba b9 b8 ip* interrupt priority b8h pt2 ps pt1 px1 pt0 px0 xx000000b iph# interrupt priority high b7h pt2h psh pt1h px1h pt0h px0h xx000000b 87 86 85 84 83 82 81 80 p0* port 0 80h ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 ffh 97 96 95 94 93 92 91 90 p1* port 1 90h t2ex t2 ffh a7 a6 a5 a4 a3 a2 a1 a0 p2* port 2 a0h ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ffh b7 b6 b5 b4 b3 b2 b1 b0 p3* port 3 b0h rd wr t1 t0 int1 int0 txd rxd ffh pcon# 1 power control 87h smod1 smod0 pof gf1 gf0 pd idl 00xx0000b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov p 000000x0b racap2h # timer 2 capture high cbh 00h racap2l # timer 2 capture low cah 00h saddr# slave address a9h 00h saden# slave address mask b9h 00h sbuf serial data buffer 99h xxxxxxxxb 9f 9e 9d 9c 9b 9a 99 98 scon* serial control 98h sm0/fe sm1 sm2 ren tb8 rb8 ti ri 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon* timer control 88h tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00h cf ce cd cc cb ca c9 c8 t2con* timer 2 control c8h tf2 exf2 rclk tclk exen2 tr2 c/t 2 cp/rl 2 00h t2mod# timer 2 mode control c9h t2oe dcen xxxxxx00b th0 timer high 0 8ch 00h th1 timer high 1 8dh 00h th2# timer high 2 cdh 00h tl0 timer low 0 8ah 00h tl1 timer low 1 8bh 00h tl2# timer low 2 cch 00h tmod timer mode 89h gate c/t m1 m0 gate c/t m1 m0 00h note: unused register bits that are not defined should not be set by the user's program. if violated, the device could function incor rectly. * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs. reserved bits. 1. reset value depends on reset source. 2. lpep low power eprom operation (otp only) philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 13 oscillator characteristics using the oscillator xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier. the pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. to drive the device from an external clock source, xtal1 should be driven while xtal2 is left unconnected. however, minimum and maximum high and low times specified in the data sheet must be observed. clock control register (ckcon) this device provides control of the 6-clock/12-clock mode by both an sfr bit (bit x2 in register ckcon and an otp bit (bit ox2). when x2 is 0, 12-clock mode is activated. by setting this bit to 1, the system is switching to 6-clock mode. having this option implemented as sfr bit, it can be accessed anytime and changed to either value. changing x2 from 0 to 1 will result in executing user code at twice the speed, since all system time intervals will be divided by 2. changing back from 6-clock to 12-clock mode will slow down running code by a factor of 2. the otp clock control bit (ox2) activates the 6-clock mode when programmed using a parallel programmer, superceding the x2 bit (ckcon.0). please also see table 2 below. table 2. ox2 clock mode bit (can only be set by parallel programmer) x2 bit (ckcon.0) cpu clock mode erased 0 12-clock mode (default) erased 1 6-clock mode programmed x 6-clock mode programmable clock-out a 50% duty cycle clock can be programmed to be output on p1.0. this pin, besides being a regular i/o pin, has two alternate functions. it can be programmed: 1. to input the external clock for timer/counter 2, or 2. to output a 50% duty cycle clock ranging from 61 hz to 4 mhz at a 16 mhz operating frequency in 12-clock mode (122 hz to 8 mhz in 6-clock mode). to configure the timer/counter 2 as a clock generator, bit c/t 2 (in t2con) must be cleared and bit t20e in t2mod must be set. bit tr2 (t2con.2) also must be set to start the timer. the clock-out frequency depends on the oscillator frequency and the reload value of timer 2 capture registers (rcap2h, rcap2l) as shown in this equation: oscillator frequency n (65536rcap2h, rcap2l) where: n = 2 in 6-clock mode, 4 in 12-clock mode. (rcap2h,rcap2l) = the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. in the clock-out mode timer 2 roll-overs will not generate an interrupt. this is similar to when it is used as a baud-rate generator. it is possible to use timer 2 as a baud-rate generator and a clock generator simultaneously. note, however, that the baud-rate and the clock-out frequency will be the same. reset a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods in 12-clock and 12 oscillator periods in 6-clock mode), while the oscillator is running. to insure a reliable power-up reset, the rst pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. after the reset, the part runs in 12-clock mode, unless it has been set to 6-clock operation using a parallel programmer. low power modes stop clock mode the static design enables the clock speed to be reduced down to 0 mhz (stopped). when the oscillator is stopped, the ram and special function registers retain their values. this mode allows step-by-step utilization and permits reduced system power consumption by lowering the clock frequency down to any value. for lowest power consumption the power down mode is suggested. idle mode in idle mode (see table 3), the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down mode to save even more power, a power down mode (see table 3) can be invoked by software. in this mode, the oscillator is stopped and the instruction that invoked power down is the last instruction executed. the on-chip ram and special function registers retain their values down to 2.0 v and care must be taken to return v cc to the minimum specified operating voltages before the power down mode is terminated. either a hardware reset or external interrupt can be used to exit from power down. reset redefines all the sfrs but does not change the on-chip ram. an external interrupt allows both the sfrs and the on-chip ram to retain their values. wupd (auxr1.3wakeup from power down) enables or disables the wakeup from power down with external interrupt. where: wupd = 0: disable wupd = 1: enable to properly terminate power down, the reset or external interrupt should not be executed before v cc is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10 ms). to terminate power down with an external interrupt, int0 or int1 must be enabled and configured as level-sensitive. holding the pin low restarts the oscillator but bringing the pin back high completes the exit. once the interrupt is serviced, the next instruction to be executed after reti will be the one following the instruction that put the device into power down. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 14 low-power eprom operation (lpep) the eprom array contains some analog circuits that are not required when v cc is less than 4 v, but are required for a v cc greater than 4 v. the lpep bit (auxr.4), when set, will powerdown these analog circuits resulting in a reduced supply current. this bit should be set only for applications that operate at a v cc less than 4 v. design consideration when the idle mode is terminated by a hardware reset, the device normally resumes program execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. on-chip hardware inhibits access to internal ram in this event, but access to the port pins is not inhibited. to eliminate the possibility of an unexpected write when idle is terminated by reset, the instruction following the one that invokes idle should not be one that writes to a port pin or to external memory. once ? mode the once (aon-circuit emulationo) mode facilitates testing and debugging of systems without the device having to be removed from the circuit. the once mode is invoked in the following way: 1. pull ale low while the device is in reset and psen is high; 2. hold ale low as rst is deactivated. while the device is in once mode, the port 0 pins go into a float state, and the other port pins and ale and psen are weakly pulled high. the oscillator circuit remains active. while the device is in this mode, an emulator or test cpu can be used to drive the circuit. normal operation is restored when a normal reset is applied. table 3. external pin status during idle and power-down modes mode program memory ale psen port 0 port 1 port 2 port 3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data timer 0 and timer 1 operation timer 0 and timer 1 the atimero or acountero function is selected by control bits c/t in the special function register tmod. these two timer/counters have four operating modes, which are selected by bit-pairs (m1, m0) in tmod. modes 0, 1, and 2 are the same for both timers/counters. mode 3 is different. the four operating modes are described in the following text. mode 0 putting either timer into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. figure 2 shows the mode 0 operation. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tfn. the counted input is enabled to the timer when trn = 1 and either gate = 0 or intn = 1. (setting gate = 1 allows the timer to be controlled by external input intn , to facilitate pulse width measurements). trn is a control bit in the special function register tcon (figure 3). the 13-bit register consists of all 8 bits of thn and the lower 5 bits of tln. the upper 3 bits of tln are indeterminate and should be ignored. setting the run flag (trn) does not clear the registers. mode 0 operation is the same for timer 0 as for timer 1. there are two different gate bits, one for timer 1 (tmod.7) and one for timer 0 (tmod.3). mode 1 mode 1 is the same as mode 0, except that the timer register is being run with all 16 bits. mode 2 mode 2 configures the timer register as an 8-bit counter (tln) with automatic reload, as shown in figure 4. overflow from tln not only sets tfn, but also reloads tln with the contents of thn, which is preset by software. the reload leaves thn unchanged. mode 2 operation is the same for timer 0 as for timer 1. mode 3 timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. the logic for mode 3 on timer 0 is shown in figure 5. tl0 uses the timer 0 control bits: c/t , gate, tr0, and tf0 as well as pin int0 . th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the atimer 1o interrupt. mode 3 is provided for applications requiring an extra 8-bit timer on the counter. with timer 0 in mode 3, an 80c51 can look like it has three timer/counters. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used by the serial port as a baud rate generator, or in fact, in any application not requiring an interrupt. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 15 gate c/t m1 m0 gate c/t m1 m0 bit symbol function tmod.3/ gate gating control when set. timer/counter ano is enabled only while aintn o pin is high and tmod.7 atrno control pin is set. when cleared timer ano is enabled whenever atrno control bit is set. tmod.2/ c/t timer or counter selector cleared for timer operation (input from internal system clock.) tmod.6 set for counter operation (input from atno input pin). m1 m0 operating 0 0 8048 timer: atlno serves as 5-bit prescaler. 0 1 16-bit timer/counter: athno and atlno are cascaded; there is no prescaler. 1 0 8-bit auto-reload timer/counter: athno holds a value which is to be reloaded into atlno each time it overflows. 1 1 (timer 0) tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only controlled by timer 1 control bits. 1 1 (timer 1) timer/counter 1 stopped. su01580 timer 1 timer 0 not bit addressable tmod address = 89h reset value = 00h 76543 2 1 0 figure 1. timer/counter 0/1 mode control (tmod) register intn pin timer n gate bit trn tln (5 bits) thn (8 bits) tfn interrupt control c/t = 0 c/t = 1 su01618 osc d* tn pin *d = 6 in 6-clock mode; d = 12 in 12-clock mode. figure 2. timer/counter 0/1 mode 0: 13-bit timer/counter philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 16 it0 bit symbol function tcon.7 tf1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or clearing the bit in software. tcon.6 tr1 timer 1 run control bit. set/cleared by software to turn timer/counter on/off. tcon.5 tf0 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine, or by clearing the bit in software. tcon.4 tr0 timer 0 run control bit. set/cleared by software to turn timer/counter on/off. tcon.3 ie1 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.2 it1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. tcon.1 ie0 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. tcon.0 it0 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. su01516 ie0 it1 ie1 tr0 tf0 tr1 tf1 bit addressable tcon address = 88h reset value = 00h 76543210 figure 3. timer/counter 0/1 control (tcon) register tln (8 bits) tfn interrupt control c/t = 0 c/t = 1 thn (8 bits) reload intn pin timer n gate bit trn su01619 osc d* tn pin *d = 6 in 6-clock mode; d = 12 in 12-clock mode. figure 4. timer/counter 0/1 mode 2: 8-bit auto-reload philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 17 tl0 (8 bits) tf0 interrupt control th0 (8 bits) tf1 interrupt control tr1 int0 pin timer 0 gate bit tr0 su01620 c/t = 0 c/t = 1 *d = 6 in 6-clock mode; d = 12 in 12-clock mode. osc d* osc d* t0 pin figure 5. timer/counter 0 mode 3: two 8-bit counters timer 2 operation timer 2 timer 2 is a 16-bit timer/counter which can operate as either an event timer or an event counter, as selected by c/t 2 in the special function register t2con (see figure 6). timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator, which are selected by bits in the t2con as shown in table 4. capture mode in the capture mode there are two options which are selected by bit exen2 in t2con. if exen2=0, then timer 2 is a 16-bit timer or counter (as selected by c/t 2 in t2con) which, upon overflowing, sets bit tf2, the timer 2 overflow bit. this bit can be used to generate an interrupt (by enabling the timer 2 interrupt bit in the ie register). if exen2=1, timer 2 operates as described above, but with the added feature that a 1-to-0 transition at external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2 (like tf2) can generate an interrupt (which vectors to the same location as timer 2 overflow interrupt. the timer 2 interrupt service routine can interrogate tf2 and exf2 to determine which event caused the interrupt). the capture mode is illustrated in figure 7 (there is no reload value for tl2 and th2 in this mode. even when a capture event occurs from t2ex, the counter keeps on counting t2ex pin transitions or osc/12 (12-clock mode) or osc/6 (6-clock mode) pulses). auto-reload mode (up or down counter) in the 16-bit auto-reload mode, timer 2 can be configured as either a timer or counter (c/t 2 in t2con), then programmed to count up or down. the counting direction is determined by bit dcen (down counter enable) which is located in the t2mod register (see figure 8). after reset, dcen=0 which means timer 2 will default to counting up. if dcen is set, timer 2 can count up or down depending on the value of the t2ex pin. figure 9 shows timer 2 which will count up automatically since dcen=0. in this mode there are two options selected by bit exen2 in t2con register. if exen2=0, then timer 2 counts up to 0ffffh and sets the tf2 (overflow flag) bit upon overflow. this causes the timer 2 registers to be reloaded with the 16-bit value in rcap2l and rcap2h. the values in rcap2l and rcap2h are preset by software. if exen2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input t2ex. this transition also sets the exf2 bit. the timer 2 interrupt, if enabled, can be generated when either tf2 or exf2 are 1. in figure 10 dcen=1 which enables timer 2 to count up or down. this mode allows pin t2ex to control the direction of count. when a logic 1 is applied at pin t2ex, timer 2 will count up. timer 2 will overflow at 0ffffh and set the tf2 flag, which can then generate an interrupt, if the interrupt is enabled. this timer overflow also causes the 16-bit value in rcap2l and rcap2h to be reloaded into the timer registers tl2 and th2. a logic 0 applied to pin t2ex causes timer 2 to count down. the timer will underflow when tl2 and th2 become equal to the value stored in rcap2l and rcap2h. a timer 2 underflow sets the tf2 flag and causes 0ffffh to be reloaded into the timer registers tl2 and th2. the external flag exf2 toggles when timer 2 underflows or overflows. this exf2 bit can be used as a 17th bit of resolution if needed. the exf2 flag does not generate an interrupt in this mode of operation. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 18 table 4. timer 2 operating modes rclk + tclk cp/rl 2 tr2 mode 0 0 1 16-bit auto-reload 0 1 1 16-bit capture 1 x 1 baud rate generator x x 0 (off) symbol position name and significance tf2 t2con.7 timer 2 overflow flag set by a timer 2 overflow and must be cleared by software. tf2 will not be set when either rclk or tclk = 1. exf2 t2con.6 timer 2 external flag set when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. when timer 2 interrupt is enabled, exf2 = 1 will cause the cpu to vector to the timer 2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in up/down counter mode (dcen = 1). rclk t2con.5 receive clock flag. when set, causes the serial port to use timer 2 overflow pulses for its receive clock in modes 1 and 3. rclk = 0 causes timer 1 overflow to be used for the receive clock. tclk t2con.4 transmit clock flag. when set, causes the serial port to use timer 2 overflow pulses for its transmit clock in modes 1 and 3. tclk = 0 causes timer 1 overflows to be used for the transmit clock. exen2 t2con.3 timer 2 external enable flag. when set, allows a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. exen2 = 0 causes timer 2 to ignore events at t2ex. tr2 t2con.2 start/stop control for timer 2. a logic 1 starts the timer. c/t 2 t2con.1 timer or counter select. (timer 2) 0 = internal timer (osc/12 in 12-clock mode or osc/6 in 6-clock mode) 1 = external event counter (falling edge triggered). cp/rl 2 t2con.0 capture/reload flag. when set, captures will occur on negative transitions at t2ex if exen2 = 1. when cleared, auto-reloads will occur either with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to auto-reload on timer 2 overflow. tf2 exf2 rclk tclk exen2 tr2 c/t 2 cp/rl 2 su01621 bit addressable t2con address = c8h reset value = 00h 7654 32 1 0 figure 6. timer/counter 2 (t2con) control register philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 19 tr2 control tl2 (8 bits) th2 (8 bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector capture su01622 c/t 2 = 0 c/t 2 = 1 *n = 6 in 6-clock mode; n = 12 in 12-clock mode. osc n* t2 pin figure 7. timer 2 in capture mode not bit addressable symbol position function e not implemented, reserved for future use.* t2oe t2mod.1 timer 2 output enable bit. dcen t2mod.0 down count enable bit. when set, this allows timer 2 to be configured as an up/down counter. e e e e e e t2oe dcen su01519 76543210 * user software should not write 1s to reserved bits. these bits may be used in future 8051 family products to invoke new featur es. in that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. the value read from a reser ved bit is indeterminate. t2mod address = 0c9h reset value = xxxx xx00b figure 8. timer 2 mode (t2mod) control register philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 20 tr2 control tl2 (8-bits) th2 (8-bits) tf2 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector reload su01623 c/t 2 = 0 c/t 2 = 1 *n = 6 in 6-clock mode; n = 12 in 12-clock mode. osc n* t2 pin figure 9. timer 2 in auto-reload mode (dcen = 0) tl2 th2 tr2 control su01624 ffh ffh rcap2l rcap2h (up counting reload value) t2ex pin tf2 interrupt count direction 1 = up 0 = down exf2 overflow (down counting reload value) toggle c/t 2 = 0 c/t 2 = 1 *n = 6 in 6-clock mode; n = 12 in 12-clock mode. osc n* t2 pin figure 10. timer 2 auto reload mode (dcen = 1) philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 21 osc n c/t 2 = 0 c/t 2 = 1 tr2 control tl2 (8 bits) th2 (8 bits) 16 rcap2l rcap2h exen2 control exf2 timer 2 interrupt t2ex pin transition detector t2 pin reload 2 a0o a1o rx clock 16 tx clock a0o a1o a0o a1o timer 1 overflow note availability of additional external interrupt. smod rclk tclk su01625 n = 1 in 6-clock mode n = 2 in 12-clock mode. figure 11. timer 2 in baud rate generator mode baud rate generator mode bits tclk and/or rclk in t2con (table 4) allow the serial port transmit and receive baud rates to be derived from either timer 1 or timer 2. when tclk= 0, timer 1 is used as the serial port transmit baud rate generator. when tclk= 1, timer 2 is used as the serial port transmit baud rate generator. rclk has the same effect for the serial port receive baud rate. with these two bits, the serial port can have different receive and transmit baud rates one generated by timer 1, the other by timer 2. figure 11 shows the timer 2 in baud rate generation mode. the baud rate generation mode is like the auto-reload mode, in that a rollover in th2 causes the timer 2 registers to be reloaded with the 16-bit value in registers rcap2h and rcap2l, which are preset by software. the baud rates in modes 1 and 3 are determined by timer 2's overflow rate given below: modes 1 and 3 baud rates timer 2 overflow rate 16 the timer can be configured for either atimero or acountero operation. in many applications, it is configured for atimero operation (c/t 2=0). timer operation is different for timer 2 when it is being used as a baud rate generator. usually, as a timer it would increment every machine cycle (i.e., 1/6 the oscillator frequency in 6-clock mode or 1/12 the oscillator frequency in 12-clock mode). as a baud rate generator, it increments at the oscillator frequency in 6-clock mode or at 1/2 the oscillator frequency in 12-clock mode. thus the baud rate formula is as follows: oscillator frequency [n [65536 (rcap2h, rcap2l)]] modes 1 and 3 baud rates = where: n = 16 in 6-clock mode, 32 in 12-clock mode. (rcap2h, rcap2l)= the content of rcap2h and rcap2l taken as a 16-bit unsigned integer. the timer 2 as a baud rate generator mode shown in figure 11 is valid only if rclk and/or tclk = 1 in t2con register. note that a rollover in th2 does not set tf2, and will not generate an interrupt. thus, the timer 2 interrupt does not have to be disabled when timer 2 is in the baud rate generator mode. also if the exen2 (t2 external enable flag) is set, a 1-to-0 transition in t2ex (timer/counter 2 trigger input) will set exf2 (t2 external flag) but will not cause a reload from (rcap2h, rcap2l) to (th2,tl2). therefore when timer 2 is in use as a baud rate generator, t2ex can be used as an additional external interrupt, if needed. when timer 2 is in the baud rate generator mode, one should not try to read or write th2 and tl2. as a baud rate generator, timer 2 is incremented every state time (osc/2) or asynchronously from pin t2; under these conditions, a read or write of th2 or tl2 may not be accurate. the rcap2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. the timer should be turned off (clear tr2) before accessing the timer 2 or rcap2 registers. table 5 shows commonly used baud rates and how they can be obtained from timer 2. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 22 table 5. timer 2 generated commonly used baud rates baud rate timer 2 12-clk mode 6-clk mode osc freq rcap2h rcap2l 375 k 750 k 12 mhz ff ff 9.6 k 19.2 k 12 mhz ff d9 4.8 k 9.6 k 12 mhz ff b2 2.4 k 4.8 k 12 mhz ff 64 1.2 k 2.4 k 12 mhz fe c8 300 600 12 mhz fb 1e 110 220 12 mhz f2 af 300 600 6 mhz fd 8f 110 220 6 mhz f9 57 summary of baud rate equations timer 2 is in baud rate generating mode. if timer 2 is being clocked through pin t2(p1.0) the baud rate is: baud rate timer 2 overflow rate 16 if timer 2 is being clocked internally, the baud rate is: baud rate f osc [n [65536 (rcap2h, rcap2l)]] where: n = 16 in 6-clock mode, 32 in 12-clock mode. f osc = oscillator frequency to obtain the reload value for rcap2h and rcap2l, the above equation can be rewritten as: rcap2h, rcap2l 65536 f osc n baud rate timer/counter 2 set-up except for the baud rate generator mode, the values given for t2con do not include the setting of the tr2 bit. therefore, bit tr2 must be set, separately, to turn the timer on. see table 6 for set-up of timer 2 as a timer. also see table 7 for set-up of timer 2 as a counter. table 6. timer 2 as a timer t2con mode internal control (note 1) external control (note 2) 16-bit auto-reload 00h 08h 16-bit capture 01h 09h baud rate generator receive and transmit same baud rate 34h 36h receive only 24h 26h transmit only 14h 16h table 7. timer 2 as a counter tmod mode internal control (note 1) external control (note 2) 16-bit 02h 0ah auto-reload 03h 0bh notes: 1. capture/reload occurs only on timer/counter overflow. 2. capture/reload occurs on timer/counter overflow and a 1-to-0 transition on t2ex (p1.1) pin except when timer 2 is used in the baud rate generator mode. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 23 full-duplex enhanced uart standard uart operation the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the register. (however, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost.) the serial port receive and transmit registers are both accessed at special function register sbuf. writing to sbuf loads the transmit register, and reading sbuf accesses a physically separate receive register. the serial port can operate in 4 modes: mode 0: serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received (lsb first). the baud rate is fixed at 1/12 the oscillator frequency in 12-clock mode or 1/6 the oscillator frequency in 6-clock mode. mode 1: 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in special function register scon. the baud rate is variable. mode 2: 11 bits are transmitted (through txd) or received (through rxd): start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8 in scon) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw) could be moved into tb8. on receive, the 9th data bit goes into rb8 in special function register scon, while the stop bit is ignored. the baud rate is programmable to either 1/32 or 1/64 the oscillator frequency in 12-clock mode or 1/16 or 1/32 the oscillator frequency in 6-clock mode. mode 3: 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except baud rate. the baud rate in mode 3 is variable. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. multiprocessor communications modes 2 and 3 have a special provision for multiprocessor communications. in these modes, 9 data bits are received. the 9th one goes into rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon. a way to use this feature in multiprocessor systems is as follows: when the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. an address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. with sm2 = 1, no slave will be interrupted by a data byte. an address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive the data bytes that will be coming. the slaves that weren't being addressed leave their sm2s set and go on about their business, ignoring the coming data bytes. sm2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive interrupt will not be activated unless a valid stop bit is received. serial port control register the serial port control and status register is the special function register scon, shown in figure 12. this register contains not only the mode selection bits, but also the 9th data bit for transmit and receive (tb8 and rb8), and the serial port interrupt bits (ti and ri). baud rates the baud rate in mode 0 is fixed: mode 0 baud rate = oscillator frequency / 12 (12-clock mode) or / 6 (6-clock mode). the baud rate in mode 2 depends on the value of bit smod in special function register pcon. if smod = 0 (which is the value on reset), and the port pins in 12-clock mode, the baud rate is 1/64 the oscillator frequency. if smod = 1, the baud rate is 1/32 the oscillator frequency. in 6-clock mode, the baud rate is 1/32 or 1/16 the oscillator frequency, respectively. mode 2 baud rate = 2 smod n (oscillator frequency) where: n = 64 in 12-clock mode, 32 in 6-clock mode the baud rates in modes 1 and 3 are determined by the timer 1 or timer 2 overflow rate. using timer 1 to generate baud rates when timer 1 is used as the baud rate generator (t2con.rclk = 0, t2con.tclk = 0), the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: mode 1, 3 baud rate = 2 smod n (timer 1 overflow rate) where: n = 32 in 12-clock mode, 16 in 6-clock mode the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either atimero or acountero operation, and in any of its 3 running modes. in the most typical applications, it is configured for atimero operation, in the auto-reload mode (high nibble of tmod = 0010b). in that case the baud rate is given by the formula: mode 1, 3 baud rate = 2 smod n oscillator frequency 12 [256(th1)] where: n = 32 in 12-clock mode, 16 in 6-clock mode one can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, and configuring the timer to run as a 16-bit timer (high nibble of tmod = 0001b), and using the timer 1 interrupt to do a 16-bit software reload. figure 13 lists various commonly used baud rates and how they can be obtained from timer 1. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 24 sm2 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1, then rl will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2=1 then ri will not be activated if a valid stop bit was no t received. in mode 0, sm2 should be 0. ren enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 in modes 2 and 3, is the 9th data bit that was received. in mode 1, it sm2=0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the o ther modes, in any serial transmission. must be cleared by software. ri receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the o ther modes, in any serial reception (except see sm2). must be cleared by software. sm0 sm1 sm2 ren tb8 rb8 ti ri where sm0, sm1 specify the serial port mode, as follows: sm0 sm1 mode description baud rate 0 0 0 shift register f osc /12 (12-clock mode) or f osc /6 (6-clock mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /64 or f osc /32 (12-clock mode) or f osc /32 or f osc /16 (6-clock mode) 1 1 3 9-bit uart variable su01626 bit addressable scon address = 98h reset value = 00h 76543 210 figure 12. serial port control (scon) register baud rate f smod timer 1 mode 12-clock mode 6-clock mode f osc smod c/t mode reload value mode 0 max 1.67 mhz 3.34 mhz 20 mhz x x x x mode 2 max 625 k 1250 k 20 mhz 1 x x x mode 1, 3 max 104.2 k 208.4 k 20 mhz 1 0 2 ffh mode 1, 3 19.2 k 38.4 k 11.059 mhz 1 0 2 fdh 9.6 k 19.2 k 11.059 mhz 0 0 2 fdh 4.8 k 9.6 k 11.059 mhz 0 0 2 fah 2.4 k 4.8 k 11.059 mhz 0 0 2 f4h 1.2 k 2.4 k 11.059 mhz 0 0 2 e8h 137.5 275 11.986 mhz 0 0 2 1dh 110 220 6 mhz 0 0 2 72h 110 220 12 mhz 0 0 1 feebh figure 13. timer 1 generated commonly used baud rates more about mode 0 serial data enters and exits through rxd. txd outputs the shift clock. 8 bits are transmitted/received: 8 data bits (lsb first). the baud rate is fixed a 1/12 the oscillator frequency (12-clock mode) or 1/6 the oscillator frequency (6-clock mode). figure 14 shows a simplified functional diagram of the serial port in mode 0, and associated timing. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal at s6p2 also loads a 1 into the 9th position of the transmit shift register and tells the tx control block to commence a transmission. the internal timing is such that one full machine cycle will elapse between awrite to sbufo and activation of send. send enables the output of the shift register to the alternate output function line of p3.0 and also enable shift clock to the alternate output function line of p3.1. shift clock is low during s3, s4, and s5 of every machine cycle, and high during s6, s1, and s2. at s6p2 of every machine cycle in which send is active, the contents of the transmit shift are shifted to the right one position. as data bits shift out to the right, zeros come in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position, is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control block to do one last shift and then deactivate send and set t1. both of these actions occur at s1p1 of the 10th machine cycle after awrite to sbuf.o reception is initiated by the condition ren = 1 and r1 = 0. at s6p2 of the next machine cycle, the rx control unit writes the bits 11111110 to the receive shift register, and in the next clock phase activates receive. receive enable shift clock to the alternate output function line of p3.1. shift clock makes transitions at s3p1 and s6p1 of every machine cycle. at s6p2 of every machine cycle in which receive is active, the contents of the receive shift register are philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 25 shifted to the left one position. the value that comes in from the right is the value that was sampled at the p3.0 pin at s5p2 of the same machine cycle. as data bits come in from the right, 1s shift out to the left. when the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the rx control block to do one last shift and load sbuf. at s1p1 of the 10th machine cycle after the write to scon that cleared ri, receive is cleared as ri is set. more about mode 1 ten bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on receive, the stop bit goes into rb8 in scon. in the 80c51 the baud rate is determined by the timer 1 or timer 2 overflow rate. figure 15 shows a simplified functional diagram of the serial port in mode 1, and associated timings for transmit receive. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads a 1 into the 9th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission actually commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the awrite to sbufo signal.) the transmission begins with activation of send which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. as data bits shift out to the right, zeros are clocked in from the left. when the msb of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just to the left of the msb, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 10th divide-by-16 rollover after awrite to sbuf.o reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written into the input shift register. resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times. the 16 states of the counter divide each bit time into 16ths. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of rxd. the value accepted is the value that was seen in at least 2 of the 3 samples. this is done for noise rejection. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. this is to provide rejection of false start bits. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated.: 1. r1 = 0, and 2. either sm2 = 0, or the received stop bit = 1. if either of these two conditions is not met, the received frame is irretrievably lost. if both conditions are met, the stop bit goes into rb8, the 8 data bits go into sbuf, and ri is activated. at this time, whether the above conditions are met or not, the unit goes back to looking for a 1-to-0 transition in rxd. more about modes 2 and 3 eleven bits are transmitted (through txd), or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9th data bit, and a stop bit (1). on transmit, the 9th data bit (tb8) can be assigned the value of 0 or 1. on receive, the 9the data bit goes into rb8 in scon. the baud rate is programmable to either 1/32 or 1/64 (12-clock mode) or 1/16 or 1/32 the oscillator frequency (6-clock mode) the oscillator frequency in mode 2. mode 3 may have a variable baud rate generated from timer 1 or timer 2. figures 16 and 17 show a functional diagram of the serial port in modes 2 and 3. the receive portion is exactly the same as in mode 1. the transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. transmission is initiated by any instruction that uses sbuf as a destination register. the awrite to sbufo signal also loads tb8 into the 9th bit position of the transmit shift register and flags the tx control unit that a transmission is requested. transmission commences at s1p1 of the machine cycle following the next rollover in the divide-by-16 counter. (thus, the bit times are synchronized to the divide-by-16 counter, not to the awrite to sbufo signal.) the transmission begins with activation of send, which puts the start bit at txd. one bit time later, data is activated, which enables the output bit of the transmit shift register to txd. the first shift pulse occurs one bit time after that. the first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. thereafter, only zeros are clocked in. thus, as data bits shift out to the right, zeros are clocked in from the left. when tb8 is at the output position of the shift register, then the stop bit is just to the left of tb8, and all positions to the left of that contain zeros. this condition flags the tx control unit to do one last shift and then deactivate send and set ti. this occurs at the 11th divide-by-16 rollover after awrite to subf.o reception is initiated by a detected 1-to-0 transition at rxd. for this purpose rxd is sampled at a rate of 16 times whatever baud rate has been established. when a transition is detected, the divide-by-16 counter is immediately reset, and 1ffh is written to the input shift register. at the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of r-d. the value accepted is the value that was seen in at least 2 of the 3 samples. if the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back to looking for another 1-to-0 transition. if the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. as data bits come in from the right, 1s shift out to the left. when the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the rx control block to do one last shift, load sbuf and rb8, and set ri. the signal to load sbuf and rb8, and to set ri, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. 1. ri = 0, and 2. either sm2 = 0, or the received 9th data bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. if both conditions are met, the received 9th data bit goes into rb8, and the first 8 data bits go into sbuf. one bit time later, whether the above conditions were met or not, the unit goes back to looking for a 1-to-0 transition at the rxd input. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 26 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send shift start s6 rx control start shift receive rx clock t1 r1 serial port interrupt 1 1 1 1 1 1 1 0 input shift register ren ri load sbuf shift shift clock rxd p3.0 alt output function txd p3.1 alt output function sbuf read sbuf 80c51 internal bus rxd p3.0 alt input function write to sbuf s6p2 send shift rxd (data out) d0 d1 d2 d3 d4 d5 d6 d7 transmit txd (shift clock) ti s3p1 s6p1 write to scon (clear ri) ri receive shift rxd (data in) d0 d1 d2 d3 d4 d5 d6 txd (shift clock) s5p2 receive d7 ale s4 . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 s6 . . . . s1 su00539 lsb lsb msb msb figure 14. serial port mode 0 philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 27 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start rx clock ri t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 timer 1 overflow smod = 1 smod = 0 shift bit detector transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rxd rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data 16 load sbuf shift 1ffh su00540 figure 15. serial port mode 1 philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 28 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start load sbuf rx clock t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 smod = 1 smod = 0 shift bit detector rxd stop bit gen. mode 2 phase 2 clock (1/2 f osc in 12-clock mode; f osc in 6-clock mode) r1 16 shift 1ffh transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data (smod is pcon.7) tb8 rb8 stop bit gen. su01627 figure 16. serial port mode 2 philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 29 80c51 internal bus sbuf zero detector d q s cl write to sbuf tx control tx clock send data start rx control start rx clock t1 serial port interrupt input shift register (9 bits) load sbuf shift sbuf read sbuf 80c51 internal bus txd tb8 16 1-to-0 transition detector sample 2 timer 1 overflow smod = 1 smod = 0 shift bit detector rxd r1 16 load sbuf shift 1ffh transmit send s1p1 shift tx clock write to sbuf start bit txd stop bit d0 d1 d2 d3 d4 d5 d6 d7 ti rx clock 16 reset start bit rxd stop bit d0 d1 d2 d3 d4 d5 d6 d7 bit detector sample times shift ri receive data tb8 rb8 stop bit gen. su00542 figure 17. serial port mode 3 philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 30 enhanced uart operation in addition to the standard operation modes, the uart can perform framing error detect by looking for missing stop bits, and automatic address recognition. the uart also fully supports multiprocessor communication. when used for framing error detect the uart looks for missing stop bits in the communication. a missing bit will set the fe bit in the scon register. the fe bit shares the scon.7 bit with sm0 and the function of scon.7 is determined by pcon.6 (smod0) (see figure 18). if smod0 is set then scon.7 functions as fe. scon.7 functions as sm0 when smod0 is cleared. when used as fe scon.7 can only be cleared by software. refer to figure 19. automatic address recognition automatic address recognition is a feature which allows the uart to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. this feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. this feature is enabled by setting the sm2 bit in scon. in the 9 bit uart modes, mode 2 and mode 3, the receive interrupt flag (ri) will be automatically set when the received byte contains either the agiveno address or the abroadcasto address. the 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. automatic address recognition is shown in figure 20. the 8 bit mode is called mode 1. in this mode the ri flag will be set if sm2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a given or broadcast address. mode 0 is the shift register mode and sm2 is ignored. using the automatic address recognition feature allows a master to selectively communicate with one or more slaves by invoking the given slave address or addresses. all of the slaves may be contacted by using the broadcast address. two special function registers are used to define the slave's address, saddr, and the address mask, saden. saden is used to define which bits in the saddr are to be used and which bits are adon't careo. the saden mask can be logically anded with the saddr to create the agiveno address which the master will use for addressing each of the slaves. use of the given address allows multiple slaves to be recognized while excluding others. the following examples will help to show the versatility of this scheme: slave 0 saddr = 1100 0000 saden = 1111 1101 given = 1100 00x0 slave 1 saddr = 1100 0000 saden = 1111 1110 given = 1100 000x in the above example saddr is the same and the saden data is used to differentiate between the two slaves. slave 0 requires a 0 in bit 0 and it ignores bit 1. slave 1 requires a 0 in bit 1 and bit 0 is ignored. a unique address for slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. a unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). thus, both could be addressed with 1100 0000. in a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: slave 0 saddr = 1100 0000 saden = 1111 1001 given = 1100 0xx0 slave 1 saddr = 1110 0000 saden = 1111 1010 given = 1110 0x0x slave 2 saddr = 1110 0000 saden = 1111 1100 given = 1110 00xx in the above example the differentiation among the 3 slaves is in the lower 3 address bits. slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. to select slaves 0 and 1 and exclude slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. the broadcast address for each slave is created by taking the logical or of saddr and saden. zeros in this result are trended as don't-cares. in most cases, interpreting the don't-cares as ones, the broadcast address will be ff hexadecimal. upon reset saddr (sfr address 0a9h) and saden (sfr address 0b9h) are leaded with 0s. this produces a given address of all adon't careso as well as a broadcast address of all adon't careso. this effectively disables the automatic addressing mode and allows the microcontroller to use standard 80c51 type uart drivers which do not make use of this feature. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 31 scon address = 98h reset value = 0000 0000b sm0/fe sm1 sm2 ren tb8 rb8 tl rl bit addressable (smod0 = 0/1)* symbol position function fe scon.7 framing error bit. this bit is set by the receiver when an invalid stop bit is detected. the fe bit is not cleared by valid frames but should be cleared by software. the smod0 bit must be set to enable access to the fe bit.* sm0 scon.7 serial port mode bit 0, (smod0 must = 0 to access bit sm0) sm1 scon.6 serial port mode bit 1 sm2 scon.5 enables the automatic address recognition feature in modes 2 or 3. if sm2 = 1 then rl will not be set unless the received 9th data bit (rb8) is 1, indicating an address, and the received byte is a given or broadcast address. in mode 1, if sm2 = 1 then rl will not be activated unless a valid stop bit was received, and the received byte is a given or broadcast address. in mode 0, sm2 should be 0. ren scon.4 enables serial reception. set by software to enable reception. clear by software to disable reception. tb8 scon.3 the 9th data bit that will be transmitted in modes 2 and 3. set or clear by software as desired. rb8 scon.2 in modes 2 and 3, the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. tl scon.1 transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. rl scon.0 receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see sm2). must be cleared by software. notes: *smod0 is located at pcon.6. **f osc = oscillator frequency su01628 76543210 sm0 sm1 mode description baud rate** 0 0 0 shift register f osc /12 (12-clk mode) or f osc /6 (6-clk mode) 0 1 1 8-bit uart variable 1 0 2 9-bit uart f osc /64 or f osc /32 or f osc /16 (6-clock mode) or f osc /32 (12-clock mode) 1 1 3 9-bit uart variable figure 18. scon: serial port control register philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 32 smod1 smod0 pof gf1 gf0 pd idl pcon (87h) sm0 / fe sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 stop bit data byte only in mode 2, 3 start bit set fe bit if stop bit is 0 (framing error) sm0 to uart mode control 0 : scon.7 = sm0 1 : scon.7 = fe su01191 figure 19. uart framing error detection sm0 sm1 sm2 ren tb8 rb8 ti ri scon (98h) d0 d1 d2 d3 d4 d5 d6 d7 d8 1 1 1 0 comparator 11 x received address d0 to d7 programmed address in uart mode 2 or mode 3 and sm2 = 1: interrupt if ren=1, rb8=1 and areceived addresso = aprogrammed addresso when own address received, clear sm2 to receive data bytes when all data bytes have been received: set sm2 to wait for next address. su00045 figure 20. uart multiprocessor communication, automatic address recognition philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 33 interrupt priority structure ie0 ie1 int0 it0 tf0 int1 it1 tf1 ri ti interrupt sources 0 1 0 1 su01521 tf2, exf2 figure 21. interrupt sources interrupts the devices described in this data sheet provide six interrupt sources. these are shown in figure 21. the external interrupts int0 and int1 can each be either level-activated or transition-activated, depending on bits it0 and it1 in register tcon. the flags that actually generate these interrupts are bits ie0 and ie1 in tcon. when an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. if the interrupt was level-activated, then the external requesting source is what controls the request flag, rather than the on-chip hardware. the timer 0 and timer 1 interrupts are generated by tf0 and tf1, which are set by a rollover in their respective timer/counter registers (except see timer 0 in mode 3). when a timer interrupt is generated, the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to. the serial port interrupt is generated by the logical or of ri and ti. neither of these flags is cleared by hardware when the service routine is vectored to. in fact, the service routine will normally have to determine whether it was ri or ti that generated the interrupt, and the bit will have to be cleared in software. all of the bits that generate interrupts can be set or cleared by software, with the same result as though it had been set or cleared by hardware. that is, interrupts can be generated or pending interrupts can be canceled in software. each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in special function register ie (figure 22). ie also contains a global disable bit, ea , which disables all interrupts at once. priority level structure each interrupt source can also be individually programmed to one of four priority levels by setting or clearing bits in special function registers ip (figure 23) and iph (figure 24). a lower-priority interrupt can itself be interrupted by a higher-priority interrupt, but not by another interrupt of the same level. a high-priority level 3 interrupt can't be interrupted by any other interrupt source. if two request of different priority levels are received simultaneously, the request of higher priority level is serviced. if requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. thus within each priority level there is a second priority structure determined by the polling sequence as follows: source priority within level 1. ie0 (external int 0) (highest) 2. tf0 (timer 0) 3. ie1 (external int 1) 4. tf1 (timer 1) 5. ri+ti (uart) 6. tf2, exf2 (timer 2) (lowest) note that the apriority within levelo structure is only used to resolve simultaneous requests of the same priority level. the ip and iph registers contain a number of unimplemented bits. user software should not write 1s to these positions, since they may be used in other 80c51 family products. how interrupts are handled the interrupt flags are sampled at s5p2 of every machine cycle. the samples are polled during the following machine cycle. if one of the flags was in a set condition at s5p2 of the preceding cycle, the polling cycle will find it and the interrupt system will generate an lcall to the appropriate service routine, provided this hardware-generated lcall is not blocked by any of the following conditions: 1. an interrupt of equal or higher priority level is already in progress. 2. the current (polling) cycle is not the final cycle in the execution of the instruction in progress. 3. the instruction in progress is reti or any write to the ie or ip registers. any of these three conditions will block the generation of the lcall to the interrupt service routine. condition 2 ensures that the instruction in progress will be completed before vectoring to any service routine. condition 3 ensures that if the instruction in progress is reti or any access to ie or ip, then at least one more instruction will be executed before any interrupt is vectored to. the polling cycle is repeated with each machine cycle, and the values polled are the values that were present at s5p2 of the previous machine cycle. note that if an interrupt flag is active but not being responded to for one of the above conditions, if the flag is not still active when the blocking condition is removed, the denied interrupt will not be serviced. in other words, the fact that the interrupt flag was once active but not serviced is not remembered. every polling cycle is new. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 34 ex0 enable bit = 1 enables the interrupt. enable bit = 0 disables it. bit symbol function ie.7 ea global disable bit. if ea = 0, all interrupts are disabled. if ea = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. ie.6 e not implemented. reserved for future use. ie.5 et2 timer 2 interrupt enable bit. ie.4 es serial port interrupt enable bit. ie.3 et1 timer 1 interrupt enable bit. ie.2 ex1 external interrupt 1 enable bit. ie.1 et0 timer 0 interrupt enable bit. ie.0 ex0 external interrupt 0 enable bit. su01522 et0 ex1 et1 es et2 e ea 0 1 2 3 4 5 6 7 ie address = 0a8h bit addressable reset value = 0x000000b figure 22. interrupt enable (ie) register px0 priority bit = 1 assigns higher priority priority bit = 0 assigns lower priority bit symbol function ip.7 e not implemented, reserved for future use. ip.6 e not implemented, reserved for future use. ip.5 pt2 timer 2 interrupt priority bit. ip.4 ps serial port interrupt priority bit. ip.3 pt1 timer 1 interrupt priority bit. ip.2 px1 external interrupt 1 priority bit. ip.1 pt0 timer 0 interrupt priority bit. ip.0 px0 external interrupt 0 priority bit. su01523 pt0 px1 pt1 ps pt2 e e 0 1 2 3 4 5 6 7 ip address = 0b8h bit addressable reset value = xx000000b figure 23. interrupt priority (ip) register px0h priority bit = 1 assigns higher priority priority bit = 0 assigns lower priority bit symbol function iph.7 e not implemented, reserved for future use. iph.6 e not implemented, reserved for future use. iph.5 pt2h timer 2 interrupt priority bit high. iph.4 psh serial port interrupt priority bit high. iph.3 pt1h timer 1 interrupt priority bit high. iph.2 px1h external interrupt 1 priority bit high. iph.1 pt0h timer 0 interrupt priority bit high. iph.0 px0h external interrupt 0 priority bit high. su01524 pt0h px1h pt1h psh pt2h e e 0 1 2 3 4 5 6 7 iph address = b7h bit addressable reset value = xx000000b figure 24. interrupt priority high (iph) register philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 35 . . . . c1 c2 c3 c4 c5 . . . . . . . . interrupts are polled long call to interrupt vector address interrupt routine e interrupt goes active . . . . . . . . . interrupt latched this is the fastest possible response when c2 is the final cycle of an instruction other than reti or an access to ie or ip. s5p2 s6 . . . . . . . . . su00546 figure 25. interrupt response timing diagram the polling cycle/lcall sequence is illustrated in figure 25. note that if an interrupt of higher priority level goes active prior to s5p2 of the machine cycle labeled c3 in figure 25, then in accordance with the above rules it will be vectored to during c5 and c6, without any instruction of the lower priority routine having been executed. thus the processor acknowledges an interrupt request by executing a hardware-generated lcall to the appropriate servicing routine. in some cases it also clears the flag that generated the interrupt, and in other cases it doesn't. it never clears the serial port flag. this has to be done in the user's software. it clears an external interrupt flag (ie0 or ie1) only if it was transition-activated. the hardware-generated lcall pushes the contents of the program counter on to the stack (but it does not save the psw) and reloads the pc with an address that depends on the source of the interrupt being vectored to, as shown in table 8. execution proceeds from that location until the reti instruction is encountered. the reti instruction informs the processor that this interrupt routine is no longer in progress, then pops the top two bytes from the stack and reloads the program counter. execution of the interrupted program continues from where it left off. note that a simple ret instruction would also have returned execution to the interrupted program, but it would have left the interrupt control system thinking an interrupt was still in progress, making future interrupts impossible. external interrupts the external sources can be programmed to be level-activated or transition-activated by setting or clearing bit it1 or it0 in register tcon. if itx = 0, external interrupt x is triggered by a detected low at the int x pin. if itx = 1, external interrupt x is edge triggered. in this mode if successive samples of the int x pin show a high in one cycle and a low in the next cycle, interrupt request flag iex in tcon is set. flag bit iex then requests the interrupt. since the external interrupt pins are sampled once each machine cycle, an input high or low should hold for at least 12 oscillator periods to ensure sampling. if the external interrupt is transition-activated, the external source has to hold the request pin high for at least one cycle, and then hold it low for at least one cycle. this is done to ensure that the transition is seen so that interrupt request flag iex will be set. iex will be automatically cleared by the cpu when the service routine is called. if the external interrupt is level-activated, the external source has to hold the request active until the requested interrupt is actually generated. then it has to deactivate the request before the interrupt service routine is completed, or else another interrupt will be generated. response time the int0 and int1 levels are inverted and latched into ie0 and ie1 at s5p2 of every machine cycle. the values are not actually polled by the circuitry until the next machine cycle. if a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. the call itself takes two cycles. thus, a minimum of three complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. figure 25 shows interrupt response timings. a longer response time would result if the request is blocked by one of the 3 previously listed conditions. if an interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine. if the instruction in progress is not in its final cycle, the additional wait time cannot be more the 3 cycles, since the longest instructions (mul and div) are only 4 cycles long, and if the instruction in progress is reti or an access to ie or ip, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is mul or div). thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 9 cycles. as previously mentioned, the derivatives described in this data sheet have a four-level interrupt structure. the corresponding registers are ie, ip and iph. (see figures 22, 23, and 24.) the iph (interrupt priority high) register makes the four-level interrupt structure possible. the function of the iph sfr is simple and when combined with the ip sfr determines the priority of each interrupt. the priority of each interrupt is determined as shown in the following table: priority bits interrupt priority level iph.x ip.x interrupt priority level 0 0 level 0 (lowest priority) 0 1 level 1 1 0 level 2 1 1 level 3 (highest priority) philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 36 an interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. if an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. if a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. when the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. table 8. interrupt table source polling priority request bits hardware clear? vector address external interrupt 0 1 ie0 n (l) 1 y (t) 2 03h timer 0 2 tf0 y 0bh external interrupt 1 3 ie1 n (l) y (t) 13h timer 1 4 tf1 y 1bh uart 5 ri, ti n 23h timer 2 6 tf2, exf2 n 2bh notes: 1. l = level activated 2. t = transition activated reduced emi all port pins have slew rate controlled outputs. this is to limit noise generated by quickly switching output signals. the slew rate is factory set to approximately 10 ns rise and fall times. reduced emi mode the ao bit (auxr.0) in the auxr register when set disables the ale output. auxr (8eh) 765432 1 0 ao auxr.0 ao turns off ale output. dual dptr the dual dptr structure (see figure 26) enables a way to specify the address of an external data memory location. there are two 16-bit dptr registers that address the external memory, and a single bit called dps = auxr1/bit0 that allows the program code to switch between them. ? new register name: auxr1# ? sfr address: a2h ? reset value: xxx000x0b auxr1 (a2h) 76543210 lpep wupd 0 dps where: dps = auxr1/bit0 = switches between dptr0 and dptr1. select reg dps dptr0 0 dptr1 1 the dps bit status should be saved by software when switching between dptr0 and dptr1. note that bit 2 is not writable and is always read as a zero. this allows the dps bit to be quickly toggled simply by executing an inc dptr instruction without affecting the wupd or lpep bits. dps dptr1 dptr0 dph (83h) dpl (82h) external data memory su00745a bit0 auxr1 figure 26. dptr instructions the instructions that refer to dptr refer to the data pointer that is currently selected using the auxr1/bit 0 register. the six instructions that use the dptr are as follows: inc dptr increments the data pointer by 1 mov dptr, #data16 loads the dptr with a 16-bit constant mov a, @ a+dptr move code byte relative to dptr to acc movx a, @ dptr move external ram (16-bit address) to acc movx @ dptr , a move acc to external ram (16-bit address) jmp @ a + dptr jump indirect relative to dptr the data pointer can be accessed on a byte-by-byte basis by specifying the low or high byte in an instruction which accesses the sfrs. see application note an458 for more details. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 37 absolute maximum ratings 1, 2, 3 parameter rating unit operating temperature under bias 0 to +70 or 40 to +85 c storage temperature range 65 to +150 c voltage on ea /v pp pin to v ss 0 to +13.0 v voltage on any other pin to v ss 0.5 to +6.5 v maximum i ol per i/o pin 15 ma power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 w notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. ac electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c clock frequency range symbol figure parameter operating mode power supply voltage min max unit 1/t clcl 31 oscillator frequency 6-clock 5 v 10% 0 30 mhz 6-clock 2.7 v to 5.5 v 0 16 mhz 12-clock 5 v 10% 0 33 mhz 12-clock 2.7 v to 5.5 v 0 16 mhz philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 38 dc electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c; v cc = 2.7 v to 5.5 v ; v ss = 0 v (16 mhz max. cpu clock) symbol parameter test conditions limits unit min typ 1 max v il input low voltage 11 4.0 v < v cc < 5.5 v 0.5 0.2 v cc 0.1 v 2.7 v < v cc < 4.0 v 0.5 0.7 v cc v v ih input high voltage (ports 0, 1, 2, 3, ea ) 0.2 v cc +0.9 v cc +0.5 v v ih1 input high voltage, xtal1, rst 11 0.7 v cc v cc +0.5 v v ol output low voltage, ports 1, 2, 8 v cc = 2.7 v; i ol = 1.6 ma 2 0.4 v v ol1 output low voltage, port 0, ale, psen 8, 7 v cc = 2.7 v; i ol = 3.2 ma 2 0.4 v v oh output high voltage, ports 1, 2, 3 3 v cc = 2.7 v; i oh = 20 a v cc 0.7 v v cc = 4.5 v; i oh = 30 a v cc 0.7 v v oh1 output high voltage (port 0 in external bus mode), ale 9 , psen 3 v cc = 2.7 v; i oh = 3.2 ma v cc 0.7 v i il logical 0 input current, ports 1, 2, 3 v in = 0.4 v 1 50 a i tl logical 1-to-0 transition current, ports 1, 2, 3 6 v in = 2.0 v; see note 4 650 a i li input leakage current, port 0 0.45 < v in < v cc 0.3 10 a i cc power supply current (see figure 34 and source code): active mode @ 16 mhz a idle mode @ 16 mhz a power-down mode or clock stopped (see figure 30 for conditions) 12 t amb = 0 c to 70 c 2 30 a t amb = 40 c to +85 c 3 50 a v ram ram keep-alive voltage 1.2 v r rst internal reset pull-down resistor 40 225 k w c io pin capacitance 10 (except ea ) 15 pf notes: 1. typical ratings are not guaranteed. values listed are based on tests conducted on limited number of samples at room temperatu re. 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. in the worst cases (capacitive loading > 100 pf), the noise pulse on the ale pin may exceed 0.8 v. in such cases, it may be des irable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5 ma and no more than two outputs exceed the test conditions. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the v cc 0.7 specification when the address bits are stabilizing. 4. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curren t reaches its maximum value when v in is approximately 2 v. 5. see figures 36 through 39 for i cc test conditions and figure 34 for i cc vs. frequency 12-clock mode characteristics: active mode (operating): i cc = 1.0 ma + 0.9 ma freq.[mhz] active mode (reset): i cc = 7.0 ma + 0.5 ma x freq.[mhz] idle mode: i cc = 1.0 ma + 0.18 ma x freq.[mhz] 6. this value applies to t amb = 0 c to +70 c. for t amb = 40 c to +85 c, i tl = 750 a. 7. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 8. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15 ma (*note: this is 85 c specification.) maximum i ol per 8-bit port: 26 ma maximum total i ol for all outputs: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 9. ale is tested to v oh1 , except when ale is off then v oh is the voltage specification. 10. pin capacitance is characterized but not tested. pin capacitance is less than 25 pf. pin capacitance of ceramic package is l ess than 15 pf (except ea is 25 pf). 11. to improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the rst pin, and a nominal 15 ns gl itch rejection circuitry has been added to the int0 and int1 pins. previous devices provided only an inherent 5 ns of glitch rejection. 12. power down mode for 3 v range: commercial temperature range typ: 0.5 a, max. 20 a; industrial temperature range typ. 1.0 a, max. 30 a; philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 39 dc electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c; v cc = 5 v 10% ; v ss = 0 v (30/33 mhz max. cpu clock) symbol parameter test conditions limits unit min typ 1 max v il input low voltage 11 4.5 v < v cc < 5.5 v 0.5 0.2 v cc 0.1 v v ih input high voltage (ports 0, 1, 2, 3, ea ) 0.2 v cc +0.9 v cc +0.5 v v ih1 input high voltage, xtal1, rst 11 0.7 v cc v cc +0.5 v v ol output low voltage, ports 1, 2, 3 8 v cc = 4.5 v; i ol = 1.6 ma 2 0.4 v v ol1 output low voltage, port 0, ale, psen 7, 8 v cc = 4.5 v; i ol = 3.2 ma 2 0.4 v v oh output high voltage, ports 1, 2, 3 3 v cc = 4.5 v; i oh = 30 a v cc 0.7 v v oh1 output high voltage (port 0 in external bus mode), ale 9 , psen 3 v cc = 4.5 v; i oh = 3.2 ma v cc 0.7 v i il logical 0 input current, ports 1, 2, 3 v in = 0.4 v 1 50 a i tl logical 1-to-0 transition current, ports 1, 2, 3 6 v in = 2.0 v; see note 4 650 a i li input leakage current, port 0 0.45 < v in < v cc 0.3 10 a i cc power supply current (see figure 34): active mode (see note 5) idle mode (see note 5) power-down mode or clock stopped (see figure 39 for conditions) t amb = 0 c to 70 c 2 30 a t amb = 40 c to +85 c 3 50 a v ram ram keep-alive voltage 1.2 v r rst internal reset pull-down resistor 40 225 k w c io pin capacitance 10 (except ea ) 15 pf notes: 1. typical ratings are not guaranteed. the values listed are at room temperature, 5 v. 2. capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the v ol s of ale and ports 1 and 3. the noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus oper ations. in the worst cases (capacitive loading > 100 pf), the noise pulse on the ale pin may exceed 0.8 v. in such cases, it may be desirable to qualify ale with a schmitt trigger, or use an address latch with a schmitt trigger strobe input. i ol can exceed these conditions provided that no single output sinks more than 5 ma and no more than two outputs exceed the test conditions. 3. capacitive loading on ports 0 and 2 may cause the v oh on ale and psen to momentarily fall below the v cc 0.7 specification when the address bits are stabilizing. 4. pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. the transition curren t reaches its maximum value when v in is approximately 2 v. 5. see figures 36 through 39 for i cc test conditions and figure 34 for i cc vs. frequency. 12-clock mode characteristics: active mode (operating): i cc(max) = 1.0 ma + 0.9 ma freq.[mhz] active mode (reset): i cc(max) = 7.0 ma + 0.5 ma x freq.[mhz] idle mode: i cc(max) = 1.0 ma + 0.18 ma freq.[mhz] 6. this value applies to t amb = 0 c to +70 c. for t amb = 40 c to +85 c, i tl = 750 ma . 7. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all other outputs = 80 pf. 8. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 15 ma (*note: this is 85 c specification.) maximum i ol per 8-bit port: 26 ma maximum total i ol for all outputs: 71 ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 9. ale is tested to v oh1 , except when ale is off then v oh is the voltage specification. 10. pin capacitance is characterized but not tested. pin capacitance is less than 25 pf. pin capacitance of ceramic package is l ess than 15 pf (except ea is 25 pf). 11. to improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the rst pin, and a nominal 15 ns gl itch rejection circuitry has been added to the int0 and int1 pins. previous devices provided only an inherent 5 ns of glitch rejection. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 40 ac electrical characteristics (12-clock mode, 5 v 10% operation) t amb = 0 c to +70 c or 40 c to +85 c ; v cc = 5 v 10%, v ss = 0 v 1,2,3,4 symbol figure parameter limits 16 mhz clock unit min max min max 1/t clcl 31 oscillator frequency 0 33 mhz t lhll 27 ale pulse width 2 t clcl 8 117 ns t avll 27 address valid to ale low t clcl 13 49.5 ns t llax 27 address hold after ale low t clcl 20 42.5 ns t lliv 27 ale low to valid instruction in 4 t clcl 35 215 ns t llpl 27 ale low to psen low t clcl 10 52.5 ns t plph 27 psen pulse width 3 t clcl 10 177.5 ns t pliv 27 psen low to valid instruction in 3 t clcl 35 152.5 ns t pxix 27 input instruction hold after psen 0 0 ns t pxiz 27 input instruction float after psen t clcl 10 52.5 ns t aviv 27 address to valid instruction in 5 t clcl 35 277.5 ns t plaz 27 psen low to address float 10 10 ns data memory t rlrh 28 rd pulse width 6 t clcl 20 355 ns t wlwh 29 wr pulse width 6 t clcl 20 355 ns t rldv 28 rd low to valid data in 5 t clcl 35 277.5 ns t rhdx 28 data hold after rd 0 0 ns t rhdz 28 data float after rd 2 t clcl 10 115 ns t lldv 28 ale low to valid data in 8 t clcl 35 465 ns t avdv 28 address to valid data in 9 t clcl 35 527.5 ns t llwl 28, 29 ale low to rd or wr low 3 t clcl 15 3 t clcl +15 172.5 202.5 ns t avwl 28, 29 address valid to wr low or rd low 4 t clcl 15 235 ns t qvwx 29 data valid to wr transition t clcl 25 37.5 ns t whqx 29 data hold after wr t clcl 15 47.5 ns t qvwh 29 data valid to wr high 7 t clcl 5 432.5 ns t rlaz 28 rd low to address float 0 0 ns t whlh 28, 29 rd or wr high to ale high t clcl 10 t clcl +10 52.5 72.5 ns external clock t chcx 31 high time 0.32 t clcl t clcl t clcx ns t clcx 31 low time 0.32 t clcl t clcl t chcx ns t clch 31 rise time 5 ns t chcl 31 fall time 5 ns shift register t xlxl 30 serial port clock cycle time 12 t clcl 750 ns t qvxh 30 output data setup to clock rising edge 10 t clcl 25 600 ns t xhqx 30 output data hold after clock rising edge 2 t clcl 15 110 ns t xhdx 30 input data hold after clock rising edge 0 0 ns t xhdv 30 clock rising edge to input data valid 10 t clcl 133 492 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all outputs = 80 pf 3. interfacing the microcontroller to devices with float time up to 45 ns is permitted. this limited bus contention will not cau se damage to port 0 drivers. 4. parts are guaranteed by design to operate down to 0 hz. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 41 ac electrical characteristics (12-clock mode, 2.7 v to 5.5 v operation) t amb = 0 c to +70 c or 40 c to +85 c ; v cc = 2.7 v to 5.5 v, v ss = 0 v 1,2,3,4 symbol figure parameter limits 16 mhz clock unit min max min max 1/t clcl 31 oscillator frequency 0 16 mhz t lhll 27 ale pulse width 2t clcl 10 115 ns t avll 27 address valid to ale low t clcl 15 47.5 ns t llax 27 address hold after ale low t clcl 25 37.5 ns t lliv 27 ale low to valid instruction in 4 t clcl 55 195 ns t llpl 27 ale low to psen low t clcl 15 47.5 ns t plph 27 psen pulse width 3 t clcl 15 172.5 ns t pliv 27 psen low to valid instruction in 3 t clcl 55 132.5 ns t pxix 27 input instruction hold after psen 0 0 ns t pxiz 27 input instruction float after psen t clcl 10 52.5 ns t aviv 27 address to valid instruction in 5 t clcl 50 262.5 ns t plaz 27 psen low to address float 10 10 ns data memory t rlrh 28 rd pulse width 6 t clcl 25 350 ns t wlwh 29 wr pulse width 6 t clcl 25 350 ns t rldv 28 rd low to valid data in 5 t clcl 50 262.5 ns t rhdx 28 data hold after rd 0 0 ns t rhdz 28 data float after rd 2 t clcl 20 105 ns t lldv 28 ale low to valid data in 8 t clcl 55 445 ns t avdv 28 address to valid data in 9 t clcl 50 512.5 ns t llwl 28, 29 ale low to rd or wr low 3 t clcl 20 3 t clcl +20 167.5 207.5 ns t avwl 28, 29 address valid to wr low or rd low 4 t clcl 20 230 ns t qvwx 29 data valid to wr transition t clcl 30 32.5 ns t whqx 29 data hold after wr t clcl 20 42.5 ns t qvwh 29 data valid to wr high 7 t clcl 10 427.5 ns t rlaz 28 rd low to address float 0 0 ns t whlh 28, 29 rd or wr high to ale high t clcl 15 t clcl +15 47.5 77.5 ns external clock t chcx 31 high time 0.32 t clcl t clcl t clcx ns t clcx 31 low time 0.32 t clcl t clcl t chcx ns t clch 31 rise time 5 ns t chcl 31 fall time 5 ns shift register t xlxl 30 serial port clock cycle time 12 t clcl 750 ns t qvxh 30 output data setup to clock rising edge 10 t clcl 25 600 ns t xhqx 30 output data hold after clock rising edge 2 t clcl 15 110 ns t xhdx 30 input data hold after clock rising edge 0 0 ns t xhdv 30 clock rising edge to input data valid 10 t clcl 133 492 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen = 100 pf, load capacitance for all outputs = 80 pf 3. interfacing the microcontroller to devices with float time up to 45 ns is permitted. this limited bus contention will not cau se damage to port 0 drivers. 4. parts are guaranteed by design to operate down to 0 hz. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 42 ac electrical characteristics (6-clock mode, 5 v 10% operation) t amb = 0 c to +70 c or 40 c to +85 c ; v cc = 5 v 10%, v ss = 0 v 1,2,3,4,5 symbol figure parameter limits 16 mhz clock unit min max min max 1/t clcl 31 oscillator frequency 0 30 mhz t lhll 27 ale pulse width t clcl 8 54.5 ns t avll 27 address valid to ale low 0.5 t clcl 13 18.25 ns t llax 27 address hold after ale low 0.5 t clcl 20 11.25 ns t lliv 27 ale low to valid instruction in 2 t clcl 35 90 ns t llpl 27 ale low to psen low 0.5 t clcl 10 21.25 ns t plph 27 psen pulse width 1.5 t clcl 10 83.75 ns t pliv 27 psen low to valid instruction in 1.5 t clcl 35 58.75 ns t pxix 27 input instruction hold after psen 0 0 ns t pxiz 27 input instruction float after psen 0.5 t clcl 10 21.25 ns t aviv 27 address to valid instruction in 2.5 t clcl 35 121.25 ns t plaz 27 psen low to address float 10 10 ns data memory t rlrh 28 rd pulse width 3 t clcl 20 167.5 ns t wlwh 29 wr pulse width 3 t clcl 20 167.5 ns t rldv 28 rd low to valid data in 2.5 t clcl 35 121.25 ns t rhdx 28 data hold after rd 0 0 ns t rhdz 28 data float after rd t clcl 10 52.5 ns t lldv 28 ale low to valid data in 4 t clcl 35 215 ns t avdv 28 address to valid data in 4.5 t clcl 35 246.25 ns t llwl 28, 29 ale low to rd or wr low 1.5 t clcl 15 1.5 t clcl +15 78.75 108.75 ns t avwl 28, 29 address valid to wr low or rd low 2 t clcl 15 110 ns t qvwx 29 data valid to wr transition 0.5 t clcl 25 6.25 ns t whqx 29 data hold after wr 0.5 t clcl 15 16.25 ns t qvwh 29 data valid to wr high 3.5 t clcl 5 213.75 ns t rlaz 28 rd low to address float 0 0 ns t whlh 28, 29 rd or wr high to ale high 0.5 t clcl 10 0.5 t clcl +10 21.25 41.25 ns external clock t chcx 31 high time 0.4 t clcl t clcl t clcx ns t clcx 31 low time 0.4 t clcl t clcl t chcx ns t clch 31 rise time 5 ns t chcl 31 fall time 5 ns shift register t xlxl 30 serial port clock cycle time 6 t clcl 375 ns t qvxh 30 output data setup to clock rising edge 5 t clcl 25 287.5 ns t xhqx 30 output data hold after clock rising edge t clcl 15 47.5 ns t xhdx 30 input data hold after clock rising edge 0 0 ns t xhdv 30 clock rising edge to input data valid 5 t clcl 133 179.5 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen =100 pf, load capacitance for all outputs = 80 pf 3. interfacing the microcontroller to devices with float time up to 45ns is permitted. this limited bus contention will not caus e damage to port 0 drivers. 4. parts are guaranteed by design to operate down to 0 hz. 5. data shown in the table are the best mathematical models for the set of measured values obtained in tests. if a particular pa rameter calculated at a customer specified frequency has a negative value, it should be considered equal to zero. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 43 ac electrical characteristics (6-clock mode, 2.7 v to 5.5 v operation) t amb = 0 c to +70 c or 40 c to +85 c ; v cc =2.7 v to 5.5 v, v ss = 0 v 1,2,3,4,5 symbol figure parameter limits 16 mhz clock unit min max min max 1/t clcl 31 oscillator frequency 0 16 mhz t lhll 27 ale pulse width t clcl 10 52.5 ns t avll 27 address valid to ale low 0.5 t clcl 15 16.25 ns t llax 27 address hold after ale low 0.5 t clcl 25 6.25 ns t lliv 27 ale low to valid instruction in 2 t clcl 55 70 ns t llpl 27 ale low to psen low 0.5 t clcl 15 16.25 ns t plph 27 psen pulse width 1.5 t clcl 15 78.75 ns t pliv 27 psen low to valid instruction in 1.5 t clcl 55 38.75 ns t pxix 27 input instruction hold after psen 0 0 ns t pxiz 27 input instruction float after psen 0.5 t clcl 10 21.25 ns t aviv 27 address to valid instruction in 2.5 t clcl 50 101.25 ns t plaz 27 psen low to address float 10 10 ns data memory t rlrh 28 rd pulse width 3 t clcl 25 162.5 ns t wlwh 29 wr pulse width 3 t clcl 25 162.5 ns t rldv 28 rd low to valid data in 2.5 t clcl 50 106.25 ns t rhdx 28 data hold after rd 0 0 ns t rhdz 28 data float after rd t clcl 20 42.5 ns t lldv 28 ale low to valid data in 4 t clcl 55 195 ns t avdv 28 address to valid data in 4.5 t clcl 50 231.25 ns t llwl 28, 29 ale low to rd or wr low 1.5 t clcl 20 1.5 t clcl +20 73.75 113.75 ns t avwl 28, 29 address valid to wr low or rd low 2 t clcl 20 105 ns t qvwx 29 data valid to wr transition 0.5 t clcl 30 1.25 ns t whqx 29 data hold after wr 0.5 t clcl 20 11.25 ns t qvwh 29 data valid to wr high 3.5 t clcl 10 208.75 ns t rlaz 28 rd low to address float 0 0 ns t whlh 28, 29 rd or wr high to ale high 0.5 t clcl 15 0.5 t clcl +15 16.25 46.25 ns external clock t chcx 31 high time 0.4 t clcl t clcl t clcx ns t clcx 31 low time 0.4 t clcl t clcl t chcx ns t clch 31 rise time 5 ns t chcl 31 fall time 5 ns shift register t xlxl 30 serial port clock cycle time 6 t clcl 375 ns t qvxh 30 output data setup to clock rising edge 5 t clcl 25 287.5 ns t xhqx 30 output data hold after clock rising edge t clcl 15 47.5 ns t xhdx 30 input data hold after clock rising edge 0 0 ns t xhdv 30 clock rising edge to input data valid 5 t clcl 133 179.5 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. 2. load capacitance for port 0, ale, and psen =100 pf, load capacitance for all outputs = 80 pf 3. interfacing the microcontroller to devices with float time up to 45ns is permitted. this limited bus contention will not caus e damage to port 0 drivers. 4. parts are guaranteed by design to operate down to 0 hz. 5. data shown in the table are the best mathematical models for the set of measured values obtained in tests. if a particular pa rameter calculated at a customer specified frequency has a negative value, it should be considered equal to zero. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 44 explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: a address c clock d input data h logic level high i instruction (program memory contents) l logic level low, or ale p psen q output data r rd signal t time v valid w wr signal x no longer a valid logic level z float examples: t avll = time for address valid to ale low. t llpl =time for ale low to psen low. t pxiz ale psen port 0 port 2 a0a15 a8a15 a0a7 a0a7 t avll t pxix t llax instr in t lhll t plph t lliv t plaz t llpl t aviv su00006 t pliv figure 27. external program memory read cycle ale psen port 0 port 2 rd a0a7 from ri or dpl data in a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t lldv t llwl t rlrh t llax t rlaz t avll t rhdx t rhdz t avwl t avdv t rldv su00025 figure 28. external data memory read cycle philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 45 t llax ale psen port 0 port 2 wr a0a7 from ri or dpl data out a0a7 from pcl instr in p2.0p2.7 or a8a15 from dpf a0a15 from pch t whlh t llwl t wlwh t avll t avwl t qvwx t whqx t qvwh su00026 figure 29. external data memory write cycle 012345678 instruction ale clock output data write to sbuf input data clear ri set ti set ri t xlxl t qvxh t xhqx t xhdx t xhdv su00027 123 0 4567 valid valid valid valid valid valid valid valid figure 30. shift register mode timing v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 31. external clock drive philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 46 v cc 0.5 0.45v 0.2v cc +0.9 0.2v cc 0.1 note: ac inputs during testing are driven at v cc 0.5 for a logic `1' and 0.45v for a logic `0'. timing measurements are made at v ih min for a logic `1' and v il max for a logic `0'. su00717 figure 32. ac testing input/output v load v load +0.1v v load 0.1v v oh 0.1v v ol +0.1v note: timing reference points for timing purposes, a port is no longer floating when a 100mv change from load voltage occurs, and begins to float when a 100mv change from the loaded v oh /v ol level occurs. i oh /i ol 20ma. su00718 figure 33. float waveform su01486 typ active mode max idle mode typ idle mode 5 481216 freq at xtal1 (mhz) 20 24 28 32 36 15 25 i cc (ma) 10 20 max active mode i cc max = 0.9 freq. + 1.0 35 30 figure 34. i cc vs. freq for 12-clock operation valid only within frequency specifications of the specified operating voltage philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 47 /* ## as31 version v2.10 / *js* / ## ## ## source file: idd_ljmp1.asm ## list file: idd_ljmp1.lst created fri apr 20 15:51:40 2001 ## ########################################################## #0000 # auxr equ 08eh #0000 # ckcon equ 08fh # # #0000 # org 0 # # ljmp_label: 0000 /75;/8e;/01; # mov auxr,#001h ; turn off ale 0003 /02;/ff;/fd; # ljmp ljmp_label ; jump to end of address space 0005 /00; # nop # #fffd # org 0fffdh # # ljmp_label: # fffd /02;/fd;ff; # ljmp ljmp_label # ; nop # # */o su01499 figure 35. source code used in measuring i dd operational philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 48 v cc p0 ea rst xtal1 xtal2 v ss v cc v cc v cc i cc (nc) clock signal su00719 figure 36. i cc test condition, active mode all other pins are disconnected v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) clock signal su00720 figure 37. i cc test condition, idle mode all other pins are disconnected v cc 0.5 0.45v 0.7v cc 0.2v cc 0.1 t chcl t clcl t clch t clcx t chcx su00009 figure 38. clock signal waveform for i cc tests in active and idle modes t clch = t chcl = 5ns v cc p0 ea rst xtal1 xtal2 v ss v cc v cc i cc (nc) su00016 figure 39. i cc test condition, power down mode all other pins are disconnected. v cc = 2 v to 5.5 v philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 49 eprom characteristics the otp devices described in this data sheet can be programmed by using a modified improved quick-pulse programming ? algorithm. it differs from older methods in the value used for v pp (programming supply voltage) and in the width and number of the ale/prog pulses. the family contains two signature bytes that can be read and used by an eprom programming system to identify the device. the signature bytes identify the device as being manufactured by philips. table 9 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. the circuit configuration and waveforms for quick-pulse programming are shown in figures 40 and 41. figure 42 shows the circuit configuration for normal program memory verification. quick-pulse programming the setup for microcontroller quick-pulse programming is shown in figure 40. note that the device is running with a 4 to 6 mhz oscillator. the reason the oscillator needs to be running is that the device is executing internal address and program data transfers. the address of the eprom location to be programmed is applied to ports 1 and 2, as shown in figure 40. the code byte to be programmed into that location is applied to port 0. rst, psen and pins of ports 2 and 3 specified in table 9 are held at the `program code data' levels indicated in table 9. the ale/prog is pulsed low 5 times as shown in figure 41. to program the encryption table, repeat the 5 pulse programming sequence for addresses 0 through 1fh, using the `pgm encryption table' levels. do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. to program the security bits, repeat the 5 pulse programming sequence using the `pgm security bit' levels. after one security bit is programmed, further programming of the code memory and encryption table is disabled. however, the other security bits can still be programmed. note that the ea /v pp pin must not be allowed to go above the maximum specified v pp level for any amount of time. even a narrow glitch above that voltage can cause permanent damage to the device. the v pp source should be well regulated and free of glitches and overshoot. program verification if security bits 2 and 3 have not been programmed, the on-chip program memory can be read out for program verification. the address of the program memory locations to be read is applied to ports 1 and 2 as shown in figure 42. the other pins are held at the `verify code data' levels indicated in table 9. the contents of the address location will be emitted on port 0. external pull-ups are required on port 0 for this operation. if the 64 byte encryption table has been programmed, the data presented at port 0 will be the exclusive nor of the program byte with one of the encryption bytes. the user will have to know the encryption table contents in order to correctly decode the verification data. the encryption table itself cannot be read out. reading the signature bytes the signature bytes are read by the same procedure as a normal verification of locations 030h and 031h, except that p3.6 and p3.7 need to be pulled to a logic low. the values are: (030h) = 15h; indicates manufacturer (philips) (031h) = 92h/97h/bbh/bdh; indicates p87c51x2/52x2/54x2/ 58x2. program/verify algorithms any algorithm in agreement with the conditions listed in table 9, and which satisfies the timing specifications, is suitable. security bits with none of the security bits programmed the code in the program memory can be verified. if the encryption table is programmed, the code will be encrypted when verified. when only security bit 1 (see table 10) is programmed, movc instructions executed from external program memory are disabled from fetching code bytes from the internal memory, ea is latched on reset and all further programming of the eprom is disabled. when security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. when all three security bits are programmed, all of the conditions above apply and all external program memory execution is disabled. encryption array 64 bytes of encryption array are initially unprogrammed (all 1s). ? trademark phrase of intel corporation. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 50 table 9. eprom programming modes mode rst psen ale/prog ea /v pp p2.7 p2.6 p3.7 p3.6 p3.3 read signature 1 0 1 1 0 0 0 0 x program code data 1 0 0* v pp 1 0 1 1 x verify code data 1 0 1 1 0 0 1 1 x pgm encryption table 1 0 0* v pp 1 0 1 0 x pgm security bit 1 1 0 0* v pp 1 1 1 1 x pgm security bit 2 1 0 0* v pp 1 1 0 0 x pgm security bit 3 1 0 0* v pp 0 1 0 1 x program to 6-clock mode 1 0 0* v pp 0 0 1 0 0 verify 6-clock 4 1 0 1 1 e 0 0 1 1 verify security bits 5 1 0 1 1 e 0 1 0 x notes: 1. `0' = valid low for that pin, `1' = valid high for that pin. 2. v pp = 12.75 v 0.25 v. 3. v cc = 5 v 10% during programming and verification. 4. bit is output on p0.4 (1 = 12x, 0 = 6x). 5. security bit one is output on p0.7. security bit two is output on p0.6. security bit three is output on p0.3. * ale/prog receives 5 programming pulses for code data (also for user array; 5 pulses for encryption or security bits) while v pp is held at 12.75 v. each programming pulse is low for 100 m s ( 10 m s) and high for a minimum of 10 m s. table 10. program security bits for eprom devices program lock bits 1, 2 sb1 sb2 sb3 protection description 1 u u u no program security features enabled. (code verify will still be encrypted by the encryption array if programmed.) 2 p u u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. 3 p p u same as 2, also verify is disabled. 4 p p p same as 3, external execution is disabled. internal data ram is not accessible. notes: 1. p programmed. u unprogrammed. 2. any other combination of the security bits is not defined. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 51 a0a7 1 1 1 46mhz +5v pgm data +12.75v 5 pulses to ground 0 1 0 a8a12 p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.5 otp su01488 figure 40. programming configuration ale/prog: ale/prog: 1 0 1 0 5 pulses t glgh = 100 m s 10 m s t ghgl = 10 m s min su00875 1234 5 see exploded view below 1 figure 41. prog waveform a0a7 1 1 1 +5v pgm data 1 1 0 0 enable 0 a8a12 p1 rst p3.6 p3.7 xtal2 xtal1 v ss v cc p0 ea /v pp ale/prog psen p2.7 p2.6 p2.0p2.5 otp su01489 46mhz figure 42. program verification philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 52 programming and verification characteristics t amb = 21 c to +27 c, v cc = 5 v 10%, v ss = 0 v (see figure 43) symbol parameter min max unit v pp programming supply voltage 12.5 13.0 v i pp programming supply current 50 1 ma 1/t clcl oscillator frequency 4 6 mhz t avgl address setup to prog low 48t clcl t ghax address hold after prog 48t clcl t dvgl data setup to prog low 48t clcl t ghdx data hold after prog 48t clcl t ehsh p2.7 (enable ) high to v pp 48t clcl t shgl v pp setup to prog low 10 m s t ghsl v pp hold after prog 10 m s t glgh prog width 90 110 m s t avqv address to data valid 48t clcl t elqz enable low to data valid 48t clcl t ehqz data float after enable 0 48t clcl t ghgl prog high to prog low 10 m s note: 1. not tested. programming * verification * address address data in data out logic 1 logic 1 logic 0 t avqv t ehqz t elqv t shgl t ghsl t glgh t ghgl t avgl t ghax t dvgl t ghdx p1.0p1.7 p2.0p2.5 p3.4 (a0 a12) port 0 p0.0 p0.7 (d0 d7) ale/prog ea /v pp p2.7 ** su01414 t ehsh notes: * for programming configuration see figure 40. for verification conditions see figure 42. ** see table 9. figure 43. programming and verification philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 53 mask rom devices security bits with none of the security bits programmed the code in the program memory can be verified. if the encryption table is programmed, the code will be encrypted when verified. when only security bit 1 (see table 11) is programmed, movc instructions executed from external program memory are disabled from fetching code bytes from the internal memory, ea is latched on reset and all further programming of the eprom is disabled. when security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled. encryption array 64 bytes (87c51), or 32 bytes (87c52/4) of encryption array are initially unprogrammed (all 1s). table 11. program security bits program lock bits 1, 2 sb1 sb2 protection description 1 u u no program security features enabled. (code verify will still be encrypted by the encryption array if programmed.) 2 p u movc instructions executed from external program memory are disabled from fetching code bytes from internal memory, ea is sampled and latched on reset, and further programming of the eprom is disabled. notes: 1. p programmed. u unprogrammed. 2. any other combination of the security bits is not defined. 80c51x2 rom code submission when submitting a rom code for the 80c51x2, the following must be specified: 1. 4 kbyte user rom data 2. 64 byte rom encryption key 3. rom security bits. address content bit(s) comment 0000h to 0fffh data 7:0 user rom data 1000h to 103fh key 7:0 rom encryption key 1040h sec 0 rom security bit 1 1040h sec 1 rom security bit 2 security bit 1: when programmed, this bit has two effects on masked rom parts: 1. external movc is disabled, and 2. ea is latched on reset. security bit 2: when programmed, this bit inhibits verify user rom. note: security bit 2 cannot be enabled unless security bit 1 is enabled. if the rom code file does not include the options, the following information must be included with the rom code. for each of the following, check the appropriate box, and send to philips along with the code: security bit #1: enabled disabled security bit #2: enabled disabled encryption: no yes if yes, must send key file. 80c52x2 rom code submission when submitting a rom code for the 80c52x2, the following must be specified: 1. 8 kbyte user rom data 2. 64 byte rom encryption key 3. rom security bits. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 54 address content bit(s) comment 0000h to 1fffh data 7:0 user rom data 2000h to 203fh key 7:0 rom encryption key 2040h sec 0 rom security bit 1 2040h sec 1 rom security bit 2 security bit 1: when programmed, this bit has two effects on masked rom parts: 1. external movc is disabled, and 2. ea is latched on reset. security bit 2: when programmed, this bit inhibits verify user rom. note: security bit 2 cannot be enabled unless security bit 1 is enabled. if the rom code file does not include the options, the following information must be included with the rom code. for each of the following, check the appropriate box, and send to philips along with the code: security bit #1: enabled disabled security bit #2: enabled disabled encryption: no yes if yes, must send key file. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 55 80c54x2 rom code submission when submitting a rom code for the 80c54x2, the following must be specified: 1. 16 kbyte user rom data 2. 64 byte rom encryption key 3. rom security bits. address content bit(s) comment 0000h to 3fffh data 7:0 user rom data 4000h to 403fh key 7:0 rom encryption key ffh = no encryption 4040h sec 0 rom security bit 1 0 = enable security 1 = disable security 4040h sec 1 rom security bit 2 0 = enable security 1 = disable security security bit 1: when programmed, this bit has two effects on masked rom parts: 1. external movc is disabled, and 2. ea is latched on reset. security bit 2: when programmed, this bit inhibits verify user rom. note: security bit 2 cannot be enabled unless security bit 1 is enabled. if the rom code file does not include the options, the following information must be included with the rom code. for each of the following, check the appropriate box, and send to philips along with the code: security bit #1: enabled disabled security bit #2: enabled disabled encryption: no yes if yes, must send key file. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 56 80c58x2 rom code submission when submitting a rom code for the 80c58x2, the following must be specified: 1. 32 kbyte user rom data 2. 64 byte rom encryption key 3. rom security bits. address content bit(s) comment 0000h to 7fffh data 7:0 user rom data 8000h to 803fh key 7:0 rom encryption key ffh = no encryption 8040h sec 0 rom security bit 1 0 = enable security 1 = disable security 8040h sec 1 rom security bit 2 0 = enable security 1 = disable security security bit 1: when programmed, this bit has two effects on masked rom parts: 1. external movc is disabled, and 2. ea is latched on reset. security bit 2: when programmed, this bit inhibits verify user rom. note: security bit 2 cannot be enabled unless security bit 1 is enabled. if the rom code file does not include the options, the following information must be included with the rom code. for each of the following, check the appropriate box, and send to philips along with the code: security bit #1: enabled disabled security bit #2: enabled disabled encryption: no yes if yes, must send key file. philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 57 dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1 philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 58 plcc44: plastic leaded chip carrier; 44 leads sot187-2 philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 59 lqfp44: plastic low profile quad flat package; 44 leads; body 10 x 10 x 1.4 mm sot389-1 philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 60 tssop38: plastic thin shrink small outline package; 38 leads; body width 4.4 mm; lead pitch 0.5 mm sot510-1 philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 61 revision history rev date description _6 20030124 product data (9397 750 10995); ecn 853-2337 29260 of 06 december 2002 modifications: ? added tssop38 package details _5 20020912 product data (9397 750 10361); ecn 853-2337 28906 of 12 september 2002 _4 20020612 product data (9397 750 09969); ecn 853-2337 28427 of 12 june 2002 _3 20020422 product data (9397 750 09779); ecn 853-2337 28059 of 22 april 2002 _2 20020219 preliminary data (9397 750 09467) _1 20010924 preliminary data (9397 750 08895); initial release philips semiconductors product data p80c3xx2; p80c5xx2; p87c5xx2 80c51 8-bit microcontroller family 4k/8k/16k/32k rom/otp, low voltage (2.7 to 5.5 v), low power, high speed (30/33 mhz) 2003 jan 24 62 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2003 all rights reserved. printed in u.s.a. date of release: 0103 document order number: 9397 750 10995 data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii |
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